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L
Horak MN, Nowick SM, Carlberg M, Vishkin U.  2011.  A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 30(4):494-507.
M
Balkan AO, Qu G, Vishkin U.  2009.  Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 17(10):1419-1432.