@article {17980,
	title = {A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors},
	journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
	volume = {30},
	year = {2011},
	month = {2011/04//},
	pages = {494 - 507},
	abstract = {A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.},
	keywords = {1.36, 800, 90, architecture;size, architectures;shared, asynchronous, benchmark, chip, chips;multiprocessor, distribution, distribution;frequency, GALS, GHz;frequency, interconnection, kernel;post-layout, layout;clock, locally-synchronous, memory, MHz;globally-asynchronous, multiple, multiprocessor;clock, multiprocessor;interface, network;mixed-timing, network;network, networks;microprocessor, networks;network, nm;circuit, Parallel, routing;network-on-chip;parallel, routing;parallel, simulation;random, synchronous, systems;, timing;low-overhead, traffic;shared-memory},
	isbn = {0278-0070},
	doi = {10.1109/TCAD.2011.2114970},
	author = {Horak,M.N. and Nowick,S.M. and Carlberg,M. and Vishkin, Uzi}
}
@article {17990,
	title = {Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism},
	journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
	volume = {17},
	year = {2009},
	month = {2009/10//},
	pages = {1419 - 1432},
	abstract = {In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 90-nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing.},
	keywords = {90, cache;single, complexity;multiprocessor, delay;single-chip, first-level, high-throughput, interconnection, low-latency, network;memory, network;shared, networks;network-on-chip;parallel, nm;wire, Parallel, parallelism;size, processing;, processor;single-chip, switch, topologies;on-chip, units;mesh-of-trees;network},
	isbn = {1063-8210},
	doi = {10.1109/TVLSI.2008.2003999},
	author = {Balkan,A.O. and Gang Qu and Vishkin, Uzi}
}
