Publications

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Kee H, Bhattacharyya SS, Wong I, Rao Y.  2010.  FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques. 2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP). :1510-1513.
Kee H, Bhattacharyya SS, Kornerup J.  2010.  Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs. 2010 International Conference on Embedded Computer Systems (SAMOS). :136-143.
Ko M-Y, Zissulescu C, Puthenpurayil S, Bhattacharyya SS, Kienhuis B, Deprettere EF.  2007.  Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Transactions on Signal Processing. 55(6):3126-3138.
S
Sane N, Kee H, Seetharaman G, Bhattacharyya SS.  2010.  Scalable representation of dataflow graph structures using topological patterns. 2010 IEEE Workshop on Signal Processing Systems (SIPS). :13-18.
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Wu H-H, Shen C-C, Bhattacharyya SS, Compton K, Schulte M, Wolf M, Zhang T.  2010.  Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays. 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR). :2121-2125.
Wu H-H, Kee H, Sane N, Plishker W, Bhattacharyya SS.  2010.  Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs. 2010 21st IEEE International Symposium on Rapid System Prototyping (RSP). :1-7.