This subsection describes the compiler generated data layout of a parallel array using . A major grid of size , where
is placed over the data array, with the constraints that both v and w are powers of two, and the lengths v and w are chosen such that the physical grid is as close to the original aspect ratio of the parallel data array as possible:
Axis 0 is divided equally among v nodes, and similarly, Axis 1 among w nodes. Each node thus receives an subgrid, or tile, of the original data array. In each node, the data is laid out in row-major order form, that is, elements in each row of the subgrid are contiguous, while elements adjacent in a column have a stride in memory by positions .