Simulation of the logic switching characteristics of hot-carrier-degraded ultra-thin SOI CMOS inverters

The switching characteristics of ultra-thin SOI CMOS inverters with hot-carrier-induced degradations are examined by using device simulations. The simulator employs a robust fixed-point iteration method to avoid conventional matrix solutions. Potential-dependent interface traps and oxide trapped charges are used to model the degradations. The effects of front and back channel degradations in an nMOS device of a CMOS inverter are investigated in steady-state and transient regimes. The nonlinear variation of interface charges cannot be simulated by using a single nMOS device alone since the transition of the inverter is also determined by the pMOS transistor. It is found that the stagnant holes generated by impact ionization have a much greater effect on the rate of the pull-down transient than that of interface charges.