VLSI architectures for multidimensional transforms

TitleVLSI architectures for multidimensional transforms
Publication TypeJournal Articles
Year of Publication1991
AuthorsChakrabarti C, JaJa JF
JournalComputers, IEEE Transactions on
Pagination1053 - 1057
Date Published1991/09//
ISBN Number0018-9340
Keywordsarchitecture;, architectures;, arithmetic;, complexity;, computational, Computer, digital, fixed-precision, linear, multidimensional, separable, transforms;, VLSI

The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N times;N times; . . . times;N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(Nd+2a) and computation time T=O(dNd/2-ab ), and achieve the AT2 bound of AT2=O(n2b 2) for constant d, where n=Nd and O lt;a les;d/2