Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation

TitleParameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
Publication TypeJournal Articles
Year of Publication2007
AuthorsKo M-Y, Zissulescu C, Puthenpurayil S, Bhattacharyya SS, Kienhuis B, Deprettere EF
JournalIEEE Transactions on Signal Processing
Pagination3126 - 3138
Date Published2007/06//
ISBN Number1053-587X
KeywordsApplication software, array signal processing, code compression methodology, compact representation, Compaction, data compression, Design automation, Digital signal processing, digital signal processing chips, DSP, DSP hardware, embedded systems, Encoding, Field programmable gate arrays, field-programmable gate arrays (FPGAs), FPGA, Hardware, hierarchical runlength encoding, high-level synthesis, Kahn process, loop-based code compaction, looping construct, parameterized loop schedules, program compilers, reconfigurable design, runlength codes, scheduling, Signal generators, Signal processing, Signal synthesis, software engineering, software implementation, static dataflow models, Very large scale integration, VLSI

In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression