%0 Journal Article %J IEEE Transactions on Signal Processing %D 2007 %T Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation %A Ming-Yung Ko %A Zissulescu,C. %A Puthenpurayil,S. %A Bhattacharyya, Shuvra S. %A Kienhuis,B. %A Deprettere,E. F %K Application software %K array signal processing %K code compression methodology %K compact representation %K Compaction %K data compression %K Design automation %K Digital signal processing %K digital signal processing chips %K DSP %K DSP hardware %K embedded systems %K Encoding %K Field programmable gate arrays %K field-programmable gate arrays (FPGAs) %K FPGA %K Hardware %K hierarchical runlength encoding %K high-level synthesis %K Kahn process %K loop-based code compaction %K looping construct %K parameterized loop schedules %K program compilers %K reconfigurable design %K runlength codes %K scheduling %K Signal generators %K Signal processing %K Signal synthesis %K software engineering %K software implementation %K static dataflow models %K Very large scale integration %K VLSI %X In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression %B IEEE Transactions on Signal Processing %V 55 %P 3126 - 3138 %8 2007/06// %@ 1053-587X %G eng %N 6 %R 10.1109/TSP.2007.893964