TY - CONF T1 - Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs T2 - 2010 International Conference on Embedded Computer Systems (SAMOS) Y1 - 2010 A1 - Kee, Hojin A1 - Bhattacharyya, Shuvra S. A1 - Kornerup, J. KW - buffer memory KW - circuit complexity KW - Complexity theory KW - Computational modeling KW - data flow graphs KW - Digital signal processing KW - digital signal processing chips KW - DSP system design KW - efficient static buffering KW - Field programmable gate arrays KW - FPGA KW - graph buffer distributions KW - integrated circuit design KW - low polynomial time complexity KW - Random access memory KW - Schedules KW - SDF graph edges KW - Signal processing systems KW - Synchronous dataflow KW - synchronous dataflow graph mapping KW - Throughput KW - throughput-optimal execution KW - throughput-optimal FPGA implementation KW - two-actor SDF graph model KW - upper bounds AB - When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flow-graph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed technique is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design. JA - 2010 International Conference on Embedded Computer Systems (SAMOS) ER -