TY - CONF
T1 - Scalable representation of dataflow graph structures using topological patterns
T2 - 2010 IEEE Workshop on Signal Processing Systems (SIPS)
Y1 - 2010
A1 - Sane, N.
A1 - Kee, Hojin
A1 - Seetharaman, G.
A1 - Bhattacharyya, Shuvra S.
KW - arrays
KW - data flow graphs
KW - Dataflow graphs
KW - DIF language
KW - Digital signal processing
KW - directed graphs
KW - DSP specification languages
KW - embedded signal processing design flows
KW - embedded systems
KW - Field programmable gate arrays
KW - graphical user interface
KW - Graphical user interfaces
KW - High-level languages
KW - modelbased design
KW - optimisation
KW - optimizations
KW - scalable dataflow graph structures representation
KW - semantics
KW - Signal processing
KW - Signal processing systems
KW - Specification languages
KW - text based languages
KW - Topological patterns
KW - Topology
KW - Transform coding
AB - Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the DIF language - a language for specifying DSP-oriented dataflow graphs - with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.
JA - 2010 IEEE Workshop on Signal Processing Systems (SIPS)
ER -