TY - JOUR T1 - Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware JF - Journal of Signal Processing Systems Y1 - 2012 A1 - Kee, Hojin A1 - Chung-Ching Shen A1 - Bhattacharyya, Shuvra S. A1 - Wong, Ian A1 - Yong Rao A1 - Kornerup, Jacob KW - 4G communication systems KW - Circuits and Systems KW - Computer Imaging, Vision, Pattern Recognition and Graphics KW - Dataflow modeling KW - Electrical Engineering KW - FPGA implementation KW - Image Processing and Computer Vision KW - Parameterized dataflow KW - pattern recognition KW - scheduling KW - Signal, Image and Speech Processing AB - In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard. VL - 66 SN - 1939-8018, 1939-8115 UR - http://link.springer.com/article/10.1007/s11265-011-0599-5 CP - 3 J1 - J Sign Process Syst ER -