TY - JOUR T1 - Prototyping scalable digital signal processing systems for radio astronomy using dataflow models JF - Radio Science Y1 - 2012 A1 - Sane, N. A1 - Ford, J. A1 - Harris, A. I. A1 - Bhattacharyya, Shuvra S. KW - dataflow models KW - digital downconverter KW - Digital signal processing KW - model-based design KW - radio astronomy KW - rapid prototyping AB - There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called theInterconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decimation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. First, we introduce and demonstrate a dataflow-based design approach using thedataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs. VL - 47 SN - 1944-799X UR - http://onlinelibrary.wiley.com/doi/10.1029/2011RS004924/abstract CP - 3 ER -