TY - JOUR T1 - VLSI implementation of a tree searched vector quantizer JF - Signal Processing, IEEE Transactions on Y1 - 1993 A1 - Kolagotla,R. K. A1 - Yu,S.-S. A1 - JaJa, Joseph F. KW - (mathematics); KW - 2 KW - 20 KW - chips; KW - coding; KW - compression; KW - data KW - design; KW - digital KW - image KW - implementation; KW - MHz; KW - micron; KW - PROCESSING KW - quantisation; KW - quantizer; KW - searched KW - signal KW - tree KW - TREES KW - vector KW - VLSI KW - VLSI; AB - The VLSI design and implementation of a tree-searched vector quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical, and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using 2 mu;m N-well process on a 7.9 times;9.2 mm die. Each processor chip contains 25000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 20 MHz VL - 41 SN - 1053-587X CP - 2 M3 - 10.1109/78.193225 ER -