TY - CONF T1 - Systematic exploitation of data parallelism in hardware synthesis of DSP applications T2 - Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on Y1 - 2004 A1 - Sen,M. A1 - Bhattacharyya, Shuvra S. KW - area-performance trade-off curve KW - automatic Verilog code generation KW - circuit optimisation KW - data flow graphs KW - data parallelism KW - dedicated hardware implementation synthesis KW - design tool KW - Digital signal processing KW - DSP applications KW - embedded systems KW - hardware description languages KW - hardware synthesis KW - high level synthesis KW - high level synthesis algorithm KW - IMAGE PROCESSING KW - PARALLEL PROCESSING KW - power consumption KW - Signal processing KW - synchronous dataflow graph KW - video processing AB - We describe an approach that we have explored for low-power synthesis and optimization of image, video, and digital signal processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in a dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and, based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit. JA - Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on VL - 5 M3 - 10.1109/ICASSP.2004.1327089 ER -