@conference {19284,
	title = {Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation},
	booktitle = {2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)},
	year = {2010},
	month = {2010},
	pages = {265 - 272},
	abstract = {This paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools - the CAL parser, TDP, and CAL2C - is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder.},
	keywords = {automated generation, automatic design flow, CAL language, CAL networks, CAL-to-C translation, CAL2C translation, coarse-grain dataflow representations, Computational modeling, data flow computing, dataflow information, Dataflow programming, decoding, Digital signal processing, Libraries, MPEG-4 reconfigurable video coding decoder implementation, parallel languages, SDF detection, synchronous dataflow detection, TDP, TDP-based static scheduling, The Dataflow interchange format Package, Transform coding, user-friendly design, video coding, video processing systems, XML, XML format},
	author = {Gu, Ruirui and Piat, J. and Raulet, M. and Janneck, J.W. and Bhattacharyya, Shuvra S.}
}
@conference {19295,
	title = {Buffer management for multi-application image processing on multi-core platforms: Analysis and case study},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1662 - 1665},
	abstract = {Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly- arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.},
	keywords = {block-based image data, buffer memory management, buffer storage, concurrently-executing image processing application, data flow computing, data flow representation, data subset, Dataflow, Digital signal processing, Energy consumption, Energy management, Engineering management, FIFO buffer sizes, Hardware, Image analysis, IMAGE PROCESSING, image processing application, image representation, interprocessor communication, memory architecture, Memory management, multiapplication image processing, multicore image processing, multiprocessing, on-chip memory, power consumption, power consumption overhead, Runtime, scheduling, set theory, shared memory, storage management chips, synchronization overhead},
	author = {Ko,Dong-Ik and Won, N. and Bhattacharyya, Shuvra S.}
}
