@article {19275,
	title = {Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware},
	journal = {Journal of Signal Processing Systems},
	volume = {66},
	year = {2012},
	month = {2012},
	pages = {285 - 301},
	abstract = {In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.},
	keywords = {4G communication systems, Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow modeling, Electrical Engineering, FPGA implementation, Image Processing and Computer Vision, Parameterized dataflow, pattern recognition, scheduling, Signal, Image and Speech Processing},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-011-0599-5},
	author = {Kee, Hojin and Chung-Ching Shen and Bhattacharyya, Shuvra S. and Wong, Ian and Yong Rao and Kornerup, Jacob}
}
@article {19272,
	title = {Exploiting Statically Schedulable Regions in Dataflow Programs},
	journal = {Journal of Signal Processing Systems},
	volume = {63},
	year = {2011},
	month = {2011},
	pages = {129 - 142},
	abstract = {Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various forms of dataflow modeling, Synchronous Dataflow (SDF) is geared towards static scheduling of computational modules, which improves system performance and predictability. However, many DSP applications do not fully conform to the restrictions of SDF modeling. More general dataflow models, such as CAL (Eker and Janneck 2003), have been developed to describe dynamically-structured DSP applications. Such generalized models can express dynamically changing functionality, but lose the powerful static scheduling capabilities provided by SDF. This paper focuses on the detection of SDF-like regions in dynamic dataflow descriptions{\textemdash}in particular, in the generalized specification framework of CAL. This is an important step for applying static scheduling techniques within a dynamic dataflow framework. Our techniques combine the advantages of different dataflow languages and tools, including CAL (Eker and Janneck 2003), DIF (Hsu et al. 2005) and CAL2C (Roquier et al. 2008). In addition to detecting SDF-like regions, we apply existing SDF scheduling techniques to exploit the static properties of these regions within enclosing dynamic dataflow models. Furthermore, we propose an optimized approach for mapping SDF-like regions onto parallel processing platforms such as multi-core processors.},
	keywords = {Cal, Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow, DIF, Electrical Engineering, Image Processing and Computer Vision, multicore processors, pattern recognition, Quasi-static scheduling, Signal, Image and Speech Processing},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-009-0445-1},
	author = {Gu, Ruirui and Janneck, J{\"o}rn W. and Raulet, Micka{\"e}l and Bhattacharyya, Shuvra S.}
}
@article {19271,
	title = {Overview of the MPEG Reconfigurable Video Coding Framework},
	journal = {Journal of Signal Processing Systems},
	volume = {63},
	year = {2011},
	month = {2011},
	pages = {251 - 263},
	abstract = {Video coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis.},
	keywords = {CAL actor language, Circuits and Systems, Code synthesis, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow programming, Electrical Engineering, Image Processing and Computer Vision, pattern recognition, Reconfigurable Video Coding, Signal, Image and Speech Processing},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-009-0399-3},
	author = {Bhattacharyya, Shuvra S. and Eker, Johan and Janneck, J{\"o}rn W. and Lucarz, Christophe and Mattavelli, Marco and Raulet, Micka{\"e}l}
}
@article {19256,
	title = {Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs},
	journal = {Journal of Signal Processing Systems},
	volume = {65},
	year = {2011},
	month = {2011},
	pages = {229 - 244},
	abstract = {Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language{\textemdash}a language for specifying DSP-oriented dataflow graphs{\textemdash}with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.},
	keywords = {Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow graphs, Electrical Engineering, High-level languages, Image Processing and Computer Vision, model-based design, pattern recognition, Signal processing systems, Signal, Image and Speech Processing, Topological patterns},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-011-0610-1},
	author = {Sane, Nimish and Kee, Hojin and Seetharaman, Gunasekaran and Bhattacharyya, Shuvra S.}
}
