@conference {17984,
	title = {Resource-Aware Compiler Prefetching for Many-Cores},
	booktitle = {Parallel and Distributed Computing (ISPDC), 2010 Ninth International Symposium on},
	year = {2010},
	month = {2010/07//},
	pages = {133 - 140},
	abstract = {Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor lighter cores with less resources. Support for hardware and software prefetch increase MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We show that in situations where not enough resources are available to issue prefetch instructions for all references in a loop, it is more beneficial to decrease the prefetch distance and prefetch for as many references as possible, rather than use a fixed prefetched distance and skip prefetching for some references, as in current approaches. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15\% and the state-of-the art GCC implementation by up to 34.79\%. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show improvements of up to 24.61\%.},
	keywords = {algorithm;memory, architecture;hardware-software, architectures;parallel, architectures;resource, aware, caches;super-scalar, compiler, compiler;Multicore, compilers;parallel, GCC-derived, level, management;, many-core, memories;storage, out-of-order, Parallel, parallelism;parallel, prefetch;loop, prefetching, prefetching;shared, processor;fine-grained, processors;multiprocessing, systems;optimising},
	doi = {10.1109/ISPDC.2010.16},
	author = {Caragea,G.C. and Tzannes,A. and Keceli,F. and Barua,R. and Vishkin, Uzi}
}
@conference {18025,
	title = {Two techniques for reconciling algorithm parallelism with memory constraints},
	booktitle = {Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures},
	series = {SPAA {\textquoteright}02},
	year = {2002},
	month = {2002///},
	pages = {95 - 98},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {The utility of algorithm parallelism for coping with increased processor to memory latencies using "latency hiding" is part of the folklore of parallel computing. Latency hiding techniques increase the traffic to memory and therefore may "hit another wall": limited bandwidth to memory. The current paper attempts to stimulate research in the following general direction: show that algorithm parallelism need not conflict with limited bandwidth.A general technique for using parallel algorithms to enhance serial implementation in the face of processor-memory latency problems is revisited. Two techniques for alleviating memory bandwidth constraints are presented. Both techniques can be incorporated in a compiler.There is often considerable parallelism in many of the algorithms which are known as useful serial algorithms. Interestingly enough, all the examples provided for the use of the two techniques come from such serial algorithms.},
	keywords = {memory systems constraints, Parallel algorithms, prefetching},
	isbn = {1-58113-529-7},
	doi = {10.1145/564870.564884},
	url = {http://doi.acm.org/10.1145/564870.564884},
	author = {Vishkin, Uzi}
}
