@article {17980,
	title = {A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors},
	journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
	volume = {30},
	year = {2011},
	month = {2011/04//},
	pages = {494 - 507},
	abstract = {A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.},
	keywords = {1.36, 800, 90, architecture;size, architectures;shared, asynchronous, benchmark, chip, chips;multiprocessor, distribution, distribution;frequency, GALS, GHz;frequency, interconnection, kernel;post-layout, layout;clock, locally-synchronous, memory, MHz;globally-asynchronous, multiple, multiprocessor;clock, multiprocessor;interface, network;mixed-timing, network;network, networks;microprocessor, networks;network, nm;circuit, Parallel, routing;network-on-chip;parallel, routing;parallel, simulation;random, synchronous, systems;, timing;low-overhead, traffic;shared-memory},
	isbn = {0278-0070},
	doi = {10.1109/TCAD.2011.2114970},
	author = {Horak,M.N. and Nowick,S.M. and Carlberg,M. and Vishkin, Uzi}
}
@conference {18017,
	title = {Arbitrate-and-move primitives for high throughput on-chip interconnection networks},
	booktitle = {Circuits and Systems, 2004. ISCAS {\textquoteright}04. Proceedings of the 2004 International Symposium on},
	volume = {2},
	year = {2004},
	month = {2004/05//},
	pages = {II - 441-4 Vol.2 - II - 441-4 Vol.2},
	abstract = {An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.},
	keywords = {8, arbiter, arbitrate-and-move, architecture;, asynchronous, balanced, binary, circuit, circuit;, circuits;, consumption;, data, explicit, interconnection, interconnections;, leaf, mesh-of-trees, multi-threading;, Multithreading, n-leaf, network;, pipeline, pipelined, power, primitive, processing;, reduced, simulation;, structures;, synchronous, synchrony, system-on-chip;, tree, tree;},
	doi = {10.1109/ISCAS.2004.1329303},
	author = {Balkan,A.O. and Gang Qu and Vishkin, Uzi}
}
