@article {17980,
	title = {A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors},
	journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
	volume = {30},
	year = {2011},
	month = {2011/04//},
	pages = {494 - 507},
	abstract = {A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.},
	keywords = {1.36, 800, 90, architecture;size, architectures;shared, asynchronous, benchmark, chip, chips;multiprocessor, distribution, distribution;frequency, GALS, GHz;frequency, interconnection, kernel;post-layout, layout;clock, locally-synchronous, memory, MHz;globally-asynchronous, multiple, multiprocessor;clock, multiprocessor;interface, network;mixed-timing, network;network, networks;microprocessor, networks;network, nm;circuit, Parallel, routing;network-on-chip;parallel, routing;parallel, simulation;random, synchronous, systems;, timing;low-overhead, traffic;shared-memory},
	isbn = {0278-0070},
	doi = {10.1109/TCAD.2011.2114970},
	author = {Horak,M.N. and Nowick,S.M. and Carlberg,M. and Vishkin, Uzi}
}
@conference {17979,
	title = {Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture},
	booktitle = {Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on},
	year = {2011},
	month = {2011/05//},
	pages = {1282 - 1291},
	abstract = {The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. This paper presents a publicly available tool chain for XMT, complete with a highly configurable cycle-accurate simulator and an optimizing compiler. The XMT tool chain has matured and has been validated to a point where its description merits publication. In particular, research and experimentation enabled by the tool chain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer{\textquoteright}s workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the dual goal of ease-of-programming and performance. The applicability of our tool chain extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the tool chain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Unobstructed by techniques such as decomposition-first and programming for locality, this environment may be useful in deferring the teaching of these techniques, when desired, to more advanced or platform-specific courses.},
	keywords = {algorithm;XMT, architecture;XMT, architectures;shared, chain;cycle-accurate, compiler;programmer, compilers;parallel, component;shared, computing;optimizing, hardware;shared, many-core, many-core;concurrency, memory, multithreading;general-purpose, PRAM, simulator;ease-of-programming;explicit, systems;, theory;multi-threading;optimising, tool, workflow;programming, XMT},
	doi = {10.1109/IPDPS.2011.270},
	author = {Keceli,F. and Tzannes,A. and Caragea,G.C. and Barua,R. and Vishkin, Uzi}
}
