@conference {14926,
	title = {A Fast Algorithm for Constructing Inverted Files on Heterogeneous Platforms},
	booktitle = {Parallel Distributed Processing Symposium (IPDPS), 2011 IEEE International},
	year = {2011},
	month = {2011/05//},
	pages = {1124 - 1134},
	abstract = {Given a collection of documents residing on a disk, we develop a new strategy for processing these documents and building the inverted files extremely fast. Our approach is tailored for a heterogeneous platform consisting of a multicore CPU and a highly multithreaded GPU. Our algorithm is based on a number of novel techniques including: (i) a high-throughput pipelined strategy that produces parallel parsed streams that are consumed at the same rate by parallel indexers, (ii) a hybrid trie and B-tree dictionary data structure in which the trie is represented by a table for fast look-up and each B-tree node contains string caches, (iii) allocation of parsed streams with frequent terms to CPU threads and the rest to GPU threads so as to match the throughput of parsed streams, and (iv) optimized CUDA indexer implementation that ensures coalesced memory accesses and effective use of shared memory. We have performed extensive tests of our algorithm on a single node (two Intel Xeon X5560 Quad-core) with two NVIDIA Tesla C1060 attached to it, and were able to achieve a throughput of more than 262 MB/s on the ClueWeb09 dataset. Similar results were obtained for widely different datasets. The throughput of our algorithm is superior to the best known algorithms reported in the literature even when compared to those run on large clusters.},
	keywords = {architecture;graphics, B-tree, C1060;central, construction;multicore, CPU;multithreaded, data, device, dictionary, equipment;coprocessors;data, files, GPU;computer, graphic, indexer;Intel, pipelined, platform;high-throughput, PROCESSING, Quad-core;NVIDIA, strategy;hybrid, structure;CUDA, structure;inverted, structures;multiprocessing, systems;, Tesla, trie, unified, unit;computer, unit;heterogeneous, X5560, Xeon},
	doi = {10.1109/IPDPS.2011.107},
	author = {Wei, Zheng and JaJa, Joseph F.}
}
@conference {14813,
	title = {MDL: a language and compiler for dynamic program instrumentation},
	booktitle = {, 1997 International Conference on Parallel Architectures and Compilation Techniques., 1997. Proceedings},
	year = {1997},
	month = {1997/11/10/14},
	pages = {201 - 212},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {We use a form of dynamic code generation, called dynamic instrumentation, to collect data about the execution of an application program. Dynamic instrumentation allows us to instrument running programs to collect performance and other types of information. The instrumentation code is generated incrementally and can be inserted and removed at any time. Our instrumentation currently runs on the SPARC, PA-RISC, Power 2, Alpha, and x86 architectures. Specification of what data to collect are written in a specialized language called the Metric Description Language, that is part of the Paradyn Parallel Performance Tools. This language allows platform independent descriptions of how to collect performance data. It also provides a concise way to specify, how to constrain performance data to particular resources such as modules, procedures, nodes, files, or message channels (or combinations of these resources). We also describe the details of how we weave instrumentation into a running program},
	keywords = {Alpha architecture, application program, application program interfaces, Application software, compiler generators, Computer science, dynamic code generation, Dynamic compiler, dynamic program instrumentation, Educational institutions, files, instrumentation code, Instruments, MDL, measurement, message channels, Message passing, Metric Description Language, modules, nodes, Operating systems, optimising compilers, PA-RISC, Paradyn Parallel Performance Tools, Parallel architectures, parallel programming, performance data, platform independent descriptions, Power 2 architecture, Power generation, procedures, program debugging, Program processors, running programs, Runtime, software metrics, SPARC, Specification languages, x86 architecture},
	isbn = {0-8186-8090-3},
	doi = {10.1109/PACT.1997.644016},
	author = {Hollingsworth, Jeffrey K and Niam, O. and Miller, B. P and Zhichen Xu and Goncalves,M. J.R and Ling Zheng}
}
@article {17311,
	title = {Optimum data base reorganization points},
	journal = {Communications of the ACM},
	volume = {16},
	year = {1973},
	month = {1973/06//},
	pages = {362 - 365},
	abstract = {In certain data base organization schemes the cost per access may increase due to structural inefficiencies caused by update. By reorganizing the data base the cost per access may be reduced. However, the high cost of a reorganization prohibits frequent reorganizations. This paper examines strategies for selecting the optimum reorganization points.},
	keywords = {data base, files, Information retrieval, reorganization},
	isbn = {0001-0782},
	doi = {10.1145/362248.362267},
	url = {http://doi.acm.org/10.1145/362248.362267},
	author = {Shneiderman, Ben}
}
