@conference {19291,
	title = {Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs},
	booktitle = {2010 21st IEEE International Symposium on Rapid System Prototyping (RSP)},
	year = {2010},
	month = {2010},
	pages = {1 - 7},
	abstract = {Parameterized Synchronous Dataflow (PSDF) has been used previously for abstract scheduling and as a model for architecting embedded software and FPGA implementations. PSDF has been shown to be attractive for these purposes due to its support for flexible dynamic reconfiguration, and efficient quasi-static scheduling. To apply PSDF techniques more deeply into the design flow, support for comprehensive functional simulation and efficient hardware mapping is important. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for developing and experimenting with dataflow-based design techniques for signal processing systems, we have developed a tool for functional simulation of PSDF specifications. This simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on this simulation tool, we also present a systematic design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems for signal processing. We demonstrate capabilities for rapid and accurate prototyping offered by our proposed design methodology, along with its novel support for PSDF-based FPGA system implementation.},
	keywords = {abstract scheduling, Computational modeling, Computer architecture, data flow graphs, dataflow based design, dataflow interchange format, design flow, design language, Digital signal processing, digital signal processing systems, dynamic parameter reconfiguration, Dynamic scheduling, efficient hardware mapping, efficient quasistatic scheduling, Embedded software, embedded systems, Field programmable gate arrays, flexible dynamic reconfiguration, FPGA based systems, FPGA implementations, functional simulation, Hardware, parameterized synchronous dataflow graphs, rapid prototyping, Schedules, scheduling, semantics, simulation tool, software package, systematic design methodology},
	author = {Wu, Hsiang-Huang and Kee, Hojin and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {14793,
	title = {EMPS: an environment for memory performance studies},
	booktitle = {Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International},
	year = {2005},
	month = {2005/04//},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper describes an overview of environment for memory performance studies (EMPS). EMPS is a framework to allow different data gathering and simulation tools to be composed together to predict the performance of parallel programs on a variety of current and future high end computing (HEC) systems. The framework seeks to combine the automated nature of direct execution simulation with the predictive capabilities of performance modeling.},
	keywords = {Application software, cache storage, Computational modeling, Concurrent computing, data gathering, Delay, digital simulation, Economic forecasting, EMP radiation effects, high end computing system, High performance computing, memory architecture, memory performance, Moore{\textquoteright}s Law, PARALLEL PROCESSING, parallel program, Predictive models, simulation tool, Writing},
	isbn = {0-7695-2312-9},
	doi = {10.1109/IPDPS.2005.196},
	author = {Hollingsworth, Jeffrey K and Snavely, A. and Sbaraglia, S. and Ekanadham, K.}
}
