@conference {19295,
	title = {Buffer management for multi-application image processing on multi-core platforms: Analysis and case study},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1662 - 1665},
	abstract = {Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly- arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.},
	keywords = {block-based image data, buffer memory management, buffer storage, concurrently-executing image processing application, data flow computing, data flow representation, data subset, Dataflow, Digital signal processing, Energy consumption, Energy management, Engineering management, FIFO buffer sizes, Hardware, Image analysis, IMAGE PROCESSING, image processing application, image representation, interprocessor communication, memory architecture, Memory management, multiapplication image processing, multicore image processing, multiprocessing, on-chip memory, power consumption, power consumption overhead, Runtime, scheduling, set theory, shared memory, storage management chips, synchronization overhead},
	author = {Ko,Dong-Ik and Won, N. and Bhattacharyya, Shuvra S.}
}
@conference {14793,
	title = {EMPS: an environment for memory performance studies},
	booktitle = {Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International},
	year = {2005},
	month = {2005/04//},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper describes an overview of environment for memory performance studies (EMPS). EMPS is a framework to allow different data gathering and simulation tools to be composed together to predict the performance of parallel programs on a variety of current and future high end computing (HEC) systems. The framework seeks to combine the automated nature of direct execution simulation with the predictive capabilities of performance modeling.},
	keywords = {Application software, cache storage, Computational modeling, Concurrent computing, data gathering, Delay, digital simulation, Economic forecasting, EMP radiation effects, high end computing system, High performance computing, memory architecture, memory performance, Moore{\textquoteright}s Law, PARALLEL PROCESSING, parallel program, Predictive models, simulation tool, Writing},
	isbn = {0-7695-2312-9},
	doi = {10.1109/IPDPS.2005.196},
	author = {Hollingsworth, Jeffrey K and Snavely, A. and Sbaraglia, S. and Ekanadham, K.}
}
