@conference {12555,
	title = {Compressive wireless arrays for bearing estimation},
	booktitle = {Acoustics, Speech and Signal Processing, 2008. ICASSP 2008. IEEE International Conference on},
	year = {2008},
	month = {2008/04/31/4},
	pages = {2497 - 2500},
	abstract = {Joint processing of sensor array outputs improves the performance of parameter estimation and hypothesis testing problems beyond the sum of the individual sensor processing results. When the sensors have high data sampling rates, arrays are tethered, creating a disadvantage for their deployment and also limiting their aperture size. In this paper, we develop the signal processing algorithms for randomly deployable wireless sensor arrays that are severely constrained in communication bandwidth. We focus on the acoustic bearing estimation problem and show that when the target bearings are modeled as a sparse vector in the angle space, low dimensional random projections of the microphone signals can be used to determine multiple source bearings by solving an <i>l</i> <sub>1</sub>-norm minimization problem. Field data results are shown where only 10 bits of information is passed from each microphone to estimate multiple target bearings.},
	keywords = {acoustic, algorithms;sparse, arrays;acoustic, arrays;hypothesis, bandwidth;compressive, bearing, Estimation, estimation;signal, estimation;sparse, matrices;vectors;wireless, minimization, networks;, problem;communication, problem;microphone, problems;joint, PROCESSING, processing;array, processing;direction-of-arrival, processing;l<sub>1</sub>-norm, sensor, signal, signals;parameter, Testing, vector;wireless, wireless},
	doi = {10.1109/ICASSP.2008.4518155},
	author = {Cevher, V. and Gurbuz, A.C. and McClellan, J.H. and Chellapa, Rama}
}
@conference {12648,
	title = {Algorithmic and architectural design methodology for particle filters in hardware},
	booktitle = {Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on},
	year = {2005},
	month = {2005/10//},
	pages = {275 - 280},
	abstract = {In this paper, we present algorithmic and architectural methodology for building particle filters in hardware. Particle filtering is a new paradigm for filtering in presence of nonGaussian nonlinear state evolution and observation models. This technique has found wide-spread application in tracking, navigation, detection problems especially in a sensing environment. So far most particle filtering implementations are not lucrative for real time problems due to excessive computational complexity involved. In this paper, we re-derive the particle filtering theory to make it more amenable to simplified VLSI implementations. Furthermore, we present and analyze pipelined architectural methodology for designing these computational blocks. Finally, we present an application using the bearing only tracking problem and evaluate the proposed architecture and algorithmic methodology.},
	keywords = {(numerical, algorithmic, architectural, architectures;, bearing, complexity;, computational, design, digital, evolution;, Filtering, filtering;, filters;, implementation;, methodology;, methods);, nonGaussian, nonlinear, only, Parallel, particle, pipeline, pipelined, problem;, processing;, state, tracking, VLSI, VLSI;},
	doi = {10.1109/ICCD.2005.20},
	author = {Sankaranarayanan,A. C and Chellapa, Rama and Srivastava, A.}
}
