@conference {19295,
	title = {Buffer management for multi-application image processing on multi-core platforms: Analysis and case study},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1662 - 1665},
	abstract = {Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly- arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.},
	keywords = {block-based image data, buffer memory management, buffer storage, concurrently-executing image processing application, data flow computing, data flow representation, data subset, Dataflow, Digital signal processing, Energy consumption, Energy management, Engineering management, FIFO buffer sizes, Hardware, Image analysis, IMAGE PROCESSING, image processing application, image representation, interprocessor communication, memory architecture, Memory management, multiapplication image processing, multicore image processing, multiprocessing, on-chip memory, power consumption, power consumption overhead, Runtime, scheduling, set theory, shared memory, storage management chips, synchronization overhead},
	author = {Ko,Dong-Ik and Won, N. and Bhattacharyya, Shuvra S.}
}
@article {12378,
	title = {Contention-conscious transaction ordering in multiprocessor DSP systems},
	journal = {IEEE Transactions on Signal Processing},
	volume = {54},
	year = {2006},
	month = {2006/02//},
	pages = {556 - 569},
	abstract = {This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.},
	keywords = {contention-conscious transaction ordering, Costs, data flow graphs, Dataflow, Delay, Digital signal processing, digital signal processing chips, Embedded system, graph-theoretic analysis, Instruments, Internet telephony, interprocessor communication, iterative dataflow graphs, iterative methods, Message passing, multiprocessor, multiprocessor DSP systems, NP-complete problem, Processor scheduling, scheduling, Signal processing, synchronization, Throughput},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2005.861074},
	author = {Khandelia,M. and Bambha,N. K and Bhattacharyya, Shuvra S.}
}
