@article {19272,
	title = {Exploiting Statically Schedulable Regions in Dataflow Programs},
	journal = {Journal of Signal Processing Systems},
	volume = {63},
	year = {2011},
	month = {2011},
	pages = {129 - 142},
	abstract = {Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various forms of dataflow modeling, Synchronous Dataflow (SDF) is geared towards static scheduling of computational modules, which improves system performance and predictability. However, many DSP applications do not fully conform to the restrictions of SDF modeling. More general dataflow models, such as CAL (Eker and Janneck 2003), have been developed to describe dynamically-structured DSP applications. Such generalized models can express dynamically changing functionality, but lose the powerful static scheduling capabilities provided by SDF. This paper focuses on the detection of SDF-like regions in dynamic dataflow descriptions{\textemdash}in particular, in the generalized specification framework of CAL. This is an important step for applying static scheduling techniques within a dynamic dataflow framework. Our techniques combine the advantages of different dataflow languages and tools, including CAL (Eker and Janneck 2003), DIF (Hsu et al. 2005) and CAL2C (Roquier et al. 2008). In addition to detecting SDF-like regions, we apply existing SDF scheduling techniques to exploit the static properties of these regions within enclosing dynamic dataflow models. Furthermore, we propose an optimized approach for mapping SDF-like regions onto parallel processing platforms such as multi-core processors.},
	keywords = {Cal, Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow, DIF, Electrical Engineering, Image Processing and Computer Vision, multicore processors, pattern recognition, Quasi-static scheduling, Signal, Image and Speech Processing},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-009-0445-1},
	author = {Gu, Ruirui and Janneck, J{\"o}rn W. and Raulet, Micka{\"e}l and Bhattacharyya, Shuvra S.}
}
@inbook {19277,
	title = {Heterogeneous Design in Functional DIF},
	booktitle = {Transactions on High-Performance Embedded Architectures and Compilers IV},
	series = {Lecture Notes in Computer Science},
	year = {2011},
	month = {2011},
	pages = {391 - 408},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Dataflow formalisms have provided designers of digital signal processing (DSP) systems with analysis and optimizations for many years. As system complexity increases, designers are relying on more types of dataflow models to describe applications while retaining these implementation benefits. The semantic range of DSP-oriented dataflow models has expanded to cover heterogeneous models and dynamic applications, but efficient design, simulation, and scheduling of such applications has not. To facilitate implementing heterogeneous applications, we utilize a new dataflow model of computation and show how actors designed in other dataflow models are directly supported by this framework, allowing system designers to immediately compose and simulate actors from different models. Using examples, we show how this approach can be applied to quickly describe and functionally simulate a heterogeneous dataflow-based application such that a designer may analyze and tune trade-offs among different models and schedules for simulation time, memory consumption, and schedule size.},
	keywords = {Arithmetic and Logic Structures, Computer Communication Networks, Dataflow, heterogeneous, Input/Output and Data Communications, Logic Design, Processor Architectures, Programming Languages, Compilers, Interpreters, Signal processing},
	isbn = {978-3-642-24567-1, 978-3-642-24568-8},
	url = {http://link.springer.com/chapter/10.1007/978-3-642-24568-8_20},
	author = {Plishker,William and Sane, Nimish and Kiemb, Mary and Bhattacharyya, Shuvra S.},
	editor = {Stenstr{\"o}m, Per}
}
@conference {19295,
	title = {Buffer management for multi-application image processing on multi-core platforms: Analysis and case study},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1662 - 1665},
	abstract = {Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly- arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.},
	keywords = {block-based image data, buffer memory management, buffer storage, concurrently-executing image processing application, data flow computing, data flow representation, data subset, Dataflow, Digital signal processing, Energy consumption, Energy management, Engineering management, FIFO buffer sizes, Hardware, Image analysis, IMAGE PROCESSING, image processing application, image representation, interprocessor communication, memory architecture, Memory management, multiapplication image processing, multicore image processing, multiprocessing, on-chip memory, power consumption, power consumption overhead, Runtime, scheduling, set theory, shared memory, storage management chips, synchronization overhead},
	author = {Ko,Dong-Ik and Won, N. and Bhattacharyya, Shuvra S.}
}
@conference {19296,
	title = {Simulating dynamic communication systems using the core functional dataflow model},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1538 - 1541},
	abstract = {The latest communication technologies invariably consist of modules with dynamic behavior. There exists a number of design tools for communication system design with their foundation in dataflow modeling semantics. These tools must not only support the functional specification of dynamic communication modules and subsystems but also provide accurate estimation of resource requirements for efficient simulation and implementation. We explore this trade-off - between flexible specification of dynamic behavior and accurate estimation of resource requirements - using a representative application employing an adaptive modulation scheme. We propose an approach for precise modeling of such applications based on a recently-introduced form of dynamic dataflow called core functional dataflow. From our proposed modeling approach, we show how parameterized looped schedules can be generated and analyzed to simulate applications with low run-time overhead as well as guaranteed bounded memory execution. We demonstrate our approach using the Advanced Design System from Agilent Technologies, Inc., which is a commercial tool for design and simulation of communication systems.},
	keywords = {adaptive modulation, Analytical models, Application software, Computational modeling, core functional dataflow model, Dataflow, dataflow modeling semantics, design tools, Digital signal processing, dynamic communication systems, functional specification, Hardware, modeling and simulation, Power system modeling, Predictive models, Processor scheduling, Production, Signal processing, software tools, wireless communication},
	author = {Sane, N. and Chia-Jui Hsu and Pino,J. L and Bhattacharyya, Shuvra S.}
}
@article {12378,
	title = {Contention-conscious transaction ordering in multiprocessor DSP systems},
	journal = {IEEE Transactions on Signal Processing},
	volume = {54},
	year = {2006},
	month = {2006/02//},
	pages = {556 - 569},
	abstract = {This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.},
	keywords = {contention-conscious transaction ordering, Costs, data flow graphs, Dataflow, Delay, Digital signal processing, digital signal processing chips, Embedded system, graph-theoretic analysis, Instruments, Internet telephony, interprocessor communication, iterative dataflow graphs, iterative methods, Message passing, multiprocessor, multiprocessor DSP systems, NP-complete problem, Processor scheduling, scheduling, Signal processing, synchronization, Throughput},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2005.861074},
	author = {Khandelia,M. and Bambha,N. K and Bhattacharyya, Shuvra S.}
}
