@conference {19281,
	title = {Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays},
	booktitle = {2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)},
	year = {2010},
	month = {2010},
	pages = {2121 - 2125},
	abstract = {Processing structures based on arrays of computational elements form an important class of architectures, which includes field programmable gate arrays (FPGAs), systolic arrays, and various forms of multicore processors. A wide variety of design methods and tools have been targeted to regular processing arrays involving homogeneous processing elements. In this paper, we introduce the concept of field programmable X arrays (FPXAs) as an abstract model for design and implementation of heterogeneous multiprocessor arrays for signal processing systems. FPXAs are abstract structures that can be targeted for implementation on application-specific integrated circuits, FPGAs, or other kinds of reconfigurable processors. FPXAs can also be mapped onto multicore processors for flexible emulation. We discuss the use of dataflow models as an integrated application representation and intermediate representation for efficient specification and mapping of signal processing systems on FPXAs. We demonstrate our proposed models and techniques with a case study involving the embedding of an application-specific FPXA system on an off-the-shelf FPGA device.},
	keywords = {application specific integrated circuits, application-specific integrated circuits, computational elements, Computer architecture, decoding, Field programmable gate arrays, field programmable X arrays, FPGA, FPXA, Integrated circuit modeling, Logic Design, microprocessor chips, multicore processors, multiprocessor arrays, real-time signal processing, reconfigurable architectures, reconfigurable processors, Routing, Signal processing, Signal processing systems, systolic arrays, Viterbi algorithm},
	author = {Wu, Hsiang-Huang and Chung-Ching Shen and Bhattacharyya, Shuvra S. and Compton, K. and Schulte, M. and Wolf, M. and Zhang, Tong}
}
@conference {19289,
	title = {Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs},
	booktitle = {2010 International Conference on Embedded Computer Systems (SAMOS)},
	year = {2010},
	month = {2010},
	pages = {136 - 143},
	abstract = {When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flow-graph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed technique is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.},
	keywords = {buffer memory, circuit complexity, Complexity theory, Computational modeling, data flow graphs, Digital signal processing, digital signal processing chips, DSP system design, efficient static buffering, Field programmable gate arrays, FPGA, graph buffer distributions, integrated circuit design, low polynomial time complexity, Random access memory, Schedules, SDF graph edges, Signal processing systems, Synchronous dataflow, synchronous dataflow graph mapping, Throughput, throughput-optimal execution, throughput-optimal FPGA implementation, two-actor SDF graph model, upper bounds},
	author = {Kee, Hojin and Bhattacharyya, Shuvra S. and Kornerup, J.}
}
@conference {19297,
	title = {FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1510 - 1513},
	abstract = {Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications. In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically. However, the potential to enable efficient hardware synthesis has been treated relatively sparsely in the literature for SDF and even more so for the newer, more general PSDF model. This paper investigates efficient FPGA-based design and implementation of the physical layer for 3GPP-Long Term Evolution (LTE), a next generation cellular standard. To capture the SDF behavior of the functional core of LTE along with higher level dynamics in the standard, we use a novel PSDF-based FPGA architecture framework. We implement our PSDF-based, LTE design framework using National Instrument{\textquoteright}s LabVIEW FPGA, a recently-introduced commercial platform for reconfigurable hardware implementation. We show that our framework can effectively model the dynamics of the LTE protocol, while also providing a synthesis framework for efficient FPGA implementation.},
	keywords = {3G mobile communication, 3GPP-long term evolution, 3GPP-LTE physical layer, 4G communication systems, Computational modeling, data flow analysis, data flow graphs, Dataflow modeling, Digital signal processing, DSP applications, Field programmable gate arrays, FPGA architecture framework, FPGA implementation, FPGA-based design, Hardware, hardware synthesis, Instruments, LabVIEW FPGA, Logic Design, LTE, next generation cellular standard, parameterized synchronous data flow technique, Pervasive computing, Physical layer, Physics computing, Production, PSDF graph, reconfigurable hardware implementation, Runtime, software synthesis, Ubiquitous Computing, ubiquitous data flow model},
	author = {Kee, Hojin and Bhattacharyya, Shuvra S. and Wong, I. and Yong Rao}
}
@conference {19291,
	title = {Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs},
	booktitle = {2010 21st IEEE International Symposium on Rapid System Prototyping (RSP)},
	year = {2010},
	month = {2010},
	pages = {1 - 7},
	abstract = {Parameterized Synchronous Dataflow (PSDF) has been used previously for abstract scheduling and as a model for architecting embedded software and FPGA implementations. PSDF has been shown to be attractive for these purposes due to its support for flexible dynamic reconfiguration, and efficient quasi-static scheduling. To apply PSDF techniques more deeply into the design flow, support for comprehensive functional simulation and efficient hardware mapping is important. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for developing and experimenting with dataflow-based design techniques for signal processing systems, we have developed a tool for functional simulation of PSDF specifications. This simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on this simulation tool, we also present a systematic design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems for signal processing. We demonstrate capabilities for rapid and accurate prototyping offered by our proposed design methodology, along with its novel support for PSDF-based FPGA system implementation.},
	keywords = {abstract scheduling, Computational modeling, Computer architecture, data flow graphs, dataflow based design, dataflow interchange format, design flow, design language, Digital signal processing, digital signal processing systems, dynamic parameter reconfiguration, Dynamic scheduling, efficient hardware mapping, efficient quasistatic scheduling, Embedded software, embedded systems, Field programmable gate arrays, flexible dynamic reconfiguration, FPGA based systems, FPGA implementations, functional simulation, Hardware, parameterized synchronous dataflow graphs, rapid prototyping, Schedules, scheduling, semantics, simulation tool, software package, systematic design methodology},
	author = {Wu, Hsiang-Huang and Kee, Hojin and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19285,
	title = {Scalable representation of dataflow graph structures using topological patterns},
	booktitle = {2010 IEEE Workshop on Signal Processing Systems (SIPS)},
	year = {2010},
	month = {2010},
	pages = {13 - 18},
	abstract = {Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the DIF language - a language for specifying DSP-oriented dataflow graphs - with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.},
	keywords = {arrays, data flow graphs, Dataflow graphs, DIF language, Digital signal processing, directed graphs, DSP specification languages, embedded signal processing design flows, embedded systems, Field programmable gate arrays, graphical user interface, Graphical user interfaces, High-level languages, modelbased design, optimisation, optimizations, scalable dataflow graph structures representation, semantics, Signal processing, Signal processing systems, Specification languages, text based languages, Topological patterns, Topology, Transform coding},
	author = {Sane, N. and Kee, Hojin and Seetharaman, G. and Bhattacharyya, Shuvra S.}
}
@article {12352,
	title = {Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation},
	journal = {IEEE Transactions on Signal Processing},
	volume = {55},
	year = {2007},
	month = {2007/06//},
	pages = {3126 - 3138},
	abstract = {In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression},
	keywords = {Application software, array signal processing, code compression methodology, compact representation, Compaction, data compression, Design automation, Digital signal processing, digital signal processing chips, DSP, DSP hardware, embedded systems, Encoding, Field programmable gate arrays, field-programmable gate arrays (FPGAs), FPGA, Hardware, hierarchical runlength encoding, high-level synthesis, Kahn process, loop-based code compaction, looping construct, parameterized loop schedules, program compilers, reconfigurable design, runlength codes, scheduling, Signal generators, Signal processing, Signal synthesis, software engineering, software implementation, static dataflow models, Very large scale integration, VLSI},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2007.893964},
	author = {Ming-Yung Ko and Zissulescu,C. and Puthenpurayil,S. and Bhattacharyya, Shuvra S. and Kienhuis,B. and Deprettere,E. F}
}
