@conference {19289,
	title = {Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs},
	booktitle = {2010 International Conference on Embedded Computer Systems (SAMOS)},
	year = {2010},
	month = {2010},
	pages = {136 - 143},
	abstract = {When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flow-graph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed technique is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.},
	keywords = {buffer memory, circuit complexity, Complexity theory, Computational modeling, data flow graphs, Digital signal processing, digital signal processing chips, DSP system design, efficient static buffering, Field programmable gate arrays, FPGA, graph buffer distributions, integrated circuit design, low polynomial time complexity, Random access memory, Schedules, SDF graph edges, Signal processing systems, Synchronous dataflow, synchronous dataflow graph mapping, Throughput, throughput-optimal execution, throughput-optimal FPGA implementation, two-actor SDF graph model, upper bounds},
	author = {Kee, Hojin and Bhattacharyya, Shuvra S. and Kornerup, J.}
}
@article {12352,
	title = {Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation},
	journal = {IEEE Transactions on Signal Processing},
	volume = {55},
	year = {2007},
	month = {2007/06//},
	pages = {3126 - 3138},
	abstract = {In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression},
	keywords = {Application software, array signal processing, code compression methodology, compact representation, Compaction, data compression, Design automation, Digital signal processing, digital signal processing chips, DSP, DSP hardware, embedded systems, Encoding, Field programmable gate arrays, field-programmable gate arrays (FPGAs), FPGA, Hardware, hierarchical runlength encoding, high-level synthesis, Kahn process, loop-based code compaction, looping construct, parameterized loop schedules, program compilers, reconfigurable design, runlength codes, scheduling, Signal generators, Signal processing, Signal synthesis, software engineering, software implementation, static dataflow models, Very large scale integration, VLSI},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2007.893964},
	author = {Ming-Yung Ko and Zissulescu,C. and Puthenpurayil,S. and Bhattacharyya, Shuvra S. and Kienhuis,B. and Deprettere,E. F}
}
@article {12378,
	title = {Contention-conscious transaction ordering in multiprocessor DSP systems},
	journal = {IEEE Transactions on Signal Processing},
	volume = {54},
	year = {2006},
	month = {2006/02//},
	pages = {556 - 569},
	abstract = {This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.},
	keywords = {contention-conscious transaction ordering, Costs, data flow graphs, Dataflow, Delay, Digital signal processing, digital signal processing chips, Embedded system, graph-theoretic analysis, Instruments, Internet telephony, interprocessor communication, iterative dataflow graphs, iterative methods, Message passing, multiprocessor, multiprocessor DSP systems, NP-complete problem, Processor scheduling, scheduling, Signal processing, synchronization, Throughput},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2005.861074},
	author = {Khandelia,M. and Bambha,N. K and Bhattacharyya, Shuvra S.}
}
