@article {15404,
	title = {Simulation of the logic switching characteristics of hot-carrier-degraded ultra-thin SOI CMOS inverters},
	journal = {Solid-State Electronics},
	volume = {39},
	year = {1996},
	month = {1996/11//},
	pages = {1669 - 1674},
	abstract = {The switching characteristics of ultra-thin SOI CMOS inverters with hot-carrier-induced degradations are examined by using device simulations. The simulator employs a robust fixed-point iteration method to avoid conventional matrix solutions. Potential-dependent interface traps and oxide trapped charges are used to model the degradations. The effects of front and back channel degradations in an nMOS device of a CMOS inverter are investigated in steady-state and transient regimes. The nonlinear variation of interface charges cannot be simulated by using a single nMOS device alone since the transition of the inverter is also determined by the pMOS transistor. It is found that the stagnant holes generated by impact ionization have a much greater effect on the rate of the pull-down transient than that of interface charges.},
	isbn = {0038-1101},
	doi = {10.1016/0038-1101(96)00073-1},
	url = {http://www.sciencedirect.com/science/article/pii/0038110196000731},
	author = {Tai,Gwo-Chung and Korman,Can E. and Mayergoyz, Issak D}
}
