@article {15032,
	title = {Systolic architectures for finite-state vector quantization},
	journal = {The Journal of VLSI Signal Processing},
	volume = {5},
	year = {1993},
	month = {1993///},
	pages = {249 - 259},
	abstract = {We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line-scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024{\texttimes}1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these processors.},
	doi = {10.1007/BF01581299},
	author = {Kolagotla,R. K. and Yu,S. S. and JaJa, Joseph F.}
}
