@conference {14807,
	title = {Data Centric Cache Measurement on the Intel ltanium 2 Processor},
	booktitle = {Proceedings of the 2004 ACM/IEEE conference on Supercomputing},
	series = {SC {\textquoteright}04},
	year = {2004},
	month = {2004///},
	pages = {58{\textendash} - 58{\textendash}},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	abstract = {Processor speed continues to increase faster than the speed of access to main memory, making effective use of memory caches more important. Information about an application{\'y}s interaction with the cache is therefore critical to performance tuning. To be most useful, tools that measure this information should relate it to the source code level data structures in an application. We describe how to gather such information by using hardware performance counters to sample cache miss addresses, and present a new tool named Cache Scope that does this using the Intel Itanium 2 performance monitors. We present experimental results concerning Cache Scope{\'y}s accuracy and perturbation of cache behavior. We also describe a case study of using Cache Scope to tune two applications, achieving 24\% and 19\% reductions in running time.},
	isbn = {0-7695-2153-3},
	doi = {http://dx.doi.org/10.1109/SC.2004.21},
	url = {http://dx.doi.org/10.1109/SC.2004.21},
	author = {Buck, Bryan R and Hollingsworth, Jeffrey K}
}
