Exploiting Statically Schedulable Regions in Dataflow Programs

TitleExploiting Statically Schedulable Regions in Dataflow Programs
Publication TypeJournal Articles
Year of Publication2011
AuthorsGu R, Janneck JW, Raulet M, Bhattacharyya SS
JournalJournal of Signal Processing Systems
Pagination129 - 142
Date Published2011
ISBN Number1939-8018, 1939-8115
KeywordsCal, Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow, DIF, Electrical Engineering, Image Processing and Computer Vision, multicore processors, pattern recognition, Quasi-static scheduling, Signal, Image and Speech Processing

Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various forms of dataflow modeling, Synchronous Dataflow (SDF) is geared towards static scheduling of computational modules, which improves system performance and predictability. However, many DSP applications do not fully conform to the restrictions of SDF modeling. More general dataflow models, such as CAL (Eker and Janneck 2003), have been developed to describe dynamically-structured DSP applications. Such generalized models can express dynamically changing functionality, but lose the powerful static scheduling capabilities provided by SDF. This paper focuses on the detection of SDF-like regions in dynamic dataflow descriptions—in particular, in the generalized specification framework of CAL. This is an important step for applying static scheduling techniques within a dynamic dataflow framework. Our techniques combine the advantages of different dataflow languages and tools, including CAL (Eker and Janneck 2003), DIF (Hsu et al. 2005) and CAL2C (Roquier et al. 2008). In addition to detecting SDF-like regions, we apply existing SDF scheduling techniques to exploit the static properties of these regions within enclosing dynamic dataflow models. Furthermore, we propose an optimized approach for mapping SDF-like regions onto parallel processing platforms such as multi-core processors.

Short TitleJ Sign Process Syst