An architectural level design methodology for embedded face detection

TitleAn architectural level design methodology for embedded face detection
Publication TypeConference Papers
Year of Publication2005
AuthorsKianzad V, Saha S, Schlessman J, Aggarwal G, Bhattacharyya SS, Wolf W, Chellappa R
Conference NameProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Date Published2005///
Conference LocationNew York, NY, USA
ISBN Number1-59593-161-9
Keywordsdesign space exploration, Face detection, platforms, reconfigurable, system-level models

Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.