Publications
2011. A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 30(4):494-507.
2009. Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 17(10):1419-1432.
2007. Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing. High-Performance Interconnects, 2007. HOTI 2007. 15th Annual IEEE Symposium on. :21-28.
2004. Arbitrate-and-move primitives for high throughput on-chip interconnection networks. Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on. 2:II-441-4Vol.2-II-441-4Vol.2.