Towards Realizing a PRAM-On-Chip Vision

TitleTowards Realizing a PRAM-On-Chip Vision
Publication TypeConference Papers
Year of Publication2007
AuthorsVishkin U
Conference NameWorkshop on Highly Parallel Processing on a Chip (HPPC)
Date Published2007///

Serial computing has become largely irrelevant for growth in computing performance at around 2003.Having already concluded that to maintain past performance growth rates, general-purpose computing must be
overhauled to incorporate parallel computing at all levels of a computer system--including the programming
model—all processor vendors put forward many-core roadmaps. They all expect exponential increase in the num-
ber of cores over at least a decade. This welcome development is also a cause for apprehension. The whole world
of computing is now facing the same general-purpose parallel computing challenge that eluded computer science
for so many years and the clock is ticking. It is becoming common knowledge that if you want your program to run
faster you will have to program for parallelism, but the vendors who set up the rules have not yet provided clear
and effective means (eg, programming models and languages) for doing that. How can application software ven-
dors be expected to make a large investment in new software developments, when they know that in a few years
they are likely to have a whole new set of options for getting much better performance?! Namely, we are already
in a problematic transition stage that slows down performance growth, and may cause a recession if it lasts too
long. Unfortunately, some industry leaders are already predicting that the transition period can last a full decade.