| Abstract | While many parallel computers have been built, it has generally been too difficult to program them. Now, all computersare effectively becoming parallel machines. Biannual doubling in the number of cores on a single chip, or faster, over the
coming decade is planned by most computer vendors. Thus, the parallel programming problem is becoming more
critical. The only known solution to the parallel programming problem in the theory of computer science is through a
parallel algorithmic theory called PRAM. Unfortunately, some of the PRAM theory assumptions regarding the
bandwidth between processors and memories did not properly reflect a parallel computer that could be built in previous
decades. Reaching memories, or other processors in a multi-processor organization, required off-chip connections
through pins on the boundary of each electric chip. Using the number of transistors that is becoming available on chip,
on-chip architectures that adequately support the PRAM are becoming possible. However, the bandwidth of off-chip
connections remains insufficient and the latency remains too high. This creates a bottleneck at the boundary of the chip
for a PRAM-On-Chip architecture. This also prevents scalability to larger “supercomputing” organizations spanning
across many processing chips that can handle massive amounts of data. Instead of connections through pins and wires,
power-efficient CMOS-compatible on-chip conversion to plasmonic nanowaveguides is introduced for improved latency
and bandwidth. Proper incorporation of our ideas offer exciting avenues to resolving the parallel programming problem,
and an alternative way for building faster, more useable and much more compact supercomputers.
|
