Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

TitleMapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Publication TypeJournal Articles
Year of Publication2012
AuthorsKee H, Shen C-C, Bhattacharyya SS, Wong I, Rao Y, Kornerup J
JournalJournal of Signal Processing Systems
Pagination285 - 301
Date Published2012
ISBN Number1939-8018, 1939-8115
Keywords4G communication systems, Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow modeling, Electrical Engineering, FPGA implementation, Image Processing and Computer Vision, Parameterized dataflow, pattern recognition, scheduling, Signal, Image and Speech Processing

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

Short TitleJ Sign Process Syst