TY - CONF T1 - Exploring the probabilistic design space of multimedia systems T2 - 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings Y1 - 2003 A1 - Shaoxiong Hua A1 - Gang Qu A1 - Bhattacharyya, Shuvra S. KW - economic system prototyping KW - embedded software implementation KW - Embedded system KW - Energy consumption KW - execution time uncertainties KW - Hardware KW - multimedia embedded systems KW - multimedia system prototyping KW - multimedia systems KW - performance requirements KW - probabilistic design space KW - rapid system prototyping KW - Real time systems KW - real-time analysis KW - reasonable execution failure tolerance KW - Resource management KW - software prototyping KW - Space exploration KW - Streaming media KW - systems analysis KW - Timing KW - Uncertainty AB - In this paper, we propose the novel concept of probabilistic design for multimedia systems and a methodology to quickly explore such design space at an early design stage. The probabilistic design is motivated by the challenge of how to design, but not over-design, multimedia embedded systems while systematically incorporating such application's performance requirements, uncertainties in execution time, and tolerance for reasonable execution failures. Our goal is to bridge the gap between real-time analysis and embedded software implementation for rapid and economic (multimedia) system prototyping. Our method takes advantage of multimedia system's unique features mentioned above to relax the rigid hardware requirements for software implementation and eventually avoid over-designing the system. JA - 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings PB - IEEE SN - 0-7695-1943-1 M3 - 10.1109/IWRSP.2003.1207053 ER - TY - CONF T1 - Performance measurement using low perturbation and high precision hardware assists T2 - , The 19th IEEE Real-Time Systems Symposium, 1998. Proceedings Y1 - 1998 A1 - Mink, A. A1 - Salamon, W. A1 - Hollingsworth, Jeffrey K A1 - Arunachalam, R. KW - Clocks KW - Computerized monitoring KW - Counting circuits KW - Debugging KW - Hardware KW - hardware performance monitor KW - high precision hardware assists KW - low perturbation KW - measurement KW - MPI message passing library KW - MultiKron hardware performance monitor KW - MultiKron PCI KW - NIST KW - online performance monitoring tools KW - Paradyn parallel performance measurement tools KW - PCI bus slot KW - performance bug KW - performance evaluation KW - performance measurement KW - program debugging KW - program testing KW - real-time systems KW - Runtime KW - Timing AB - We present the design and implementation of MultiKron PCI, a hardware performance monitor that can be plugged into any computer with a free PCI bus slot. The monitor provides a series of high-resolution timers, and the ability to monitor the utilization of the PCI bus. We also demonstrate how the monitor can be integrated with online performance monitoring tools such as the Paradyn parallel performance measurement tools to improve the overhead of key timer operations by a factor of 25. In addition, we present a series of case studies using the MultiKron hardware performance monitor to measure and tune high-performance parallel completing applications. By using the monitor, we were able to find and correct a performance bug in a popular implementation of the MPI message passing library that caused some communication primitives to run at one half their potential speed JA - , The 19th IEEE Real-Time Systems Symposium, 1998. Proceedings PB - IEEE SN - 0-8186-9212-X M3 - 10.1109/REAL.1998.739771 ER - TY - CONF T1 - Verifying an intelligent structural control system: a case study T2 - Real-Time Systems Symposium, 1994., Proceedings. Y1 - 1994 A1 - Elseaidy,W. M A1 - Cleaveland, Rance A1 - Baugh,J. W. KW - automatic verification tool KW - case study KW - Concurrency Workbench KW - Distributed computing KW - Distributed control KW - distributed processing KW - finite automata KW - finite-state processes KW - formal verification KW - graphical specification language KW - high-level design KW - intelligent control KW - intelligent structural control system verification KW - Logic KW - Modechart KW - Process algebra KW - Real time systems KW - real-time systems KW - Specification languages KW - structural engineering computing KW - temporal logic KW - temporal process algebra KW - time-varying systems KW - Timing KW - timing properties KW - visual languages AB - Describes the formal verification of the timing properties of the design of an intelligent structural control system using the Concurrency Workbench, an automatic verification tool for finite-state processes. The high-level design of the system is first given in Modechart, a graphical specification language for real-time systems, and then translated into a temporal process algebra supported by the Workbench. The facilities provided by this tool are then used to analyze the system and ultimately show it to be correct JA - Real-Time Systems Symposium, 1994., Proceedings. PB - IEEE SN - 0-8186-6600-5 M3 - 10.1109/REAL.1994.342708 ER - TY - CONF T1 - RTSL: a language for real-time schedulability analysis T2 - Real-Time Systems Symposium, 1993., Proceedings. Y1 - 1993 A1 - Fredette,A. N A1 - Cleaveland, Rance KW - Algebra KW - Algorithm design and analysis KW - Dynamic scheduling KW - Failure analysis KW - finite state machines KW - finite state systems KW - formal logic KW - formal semantics KW - functional behavior KW - generalized approach KW - generalized schedulability analysis technique KW - Process algebra KW - Processor scheduling KW - reachable state space KW - Real time systems KW - real-time schedulability analysis KW - Real-Time Specification Language KW - real-time systems KW - RTSL KW - scheduling KW - Scheduling algorithm KW - scheduling discipline KW - Specification languages KW - state-based analysis KW - State-space methods KW - Time factors KW - Timing KW - timing behavior KW - timing constraints KW - timing exceptions AB - The paper develops a generalized approach to schedulability analysis that is mathematically founded in a process algebra called RTSL. Within RTSL one may describe the functional behavior, timing behavior, timing constraints (or deadlines), and scheduling discipline for real-time systems. The formal semantics of RTSL then allows the reachable state space of finite state systems to be automatically generated and searched for timing exceptions. We provide a generalized schedulability analysis technique to perform this state-based analysis JA - Real-Time Systems Symposium, 1993., Proceedings. PB - IEEE SN - 0-8186-4480-X M3 - 10.1109/REAL.1993.393489 ER - TY - CONF T1 - A theory of testing for real-time T2 - , Proceedings of Sixth Annual IEEE Symposium on Logic in Computer Science, 1991. LICS '91 Y1 - 1991 A1 - Cleaveland, Rance A1 - Zwarico,A. E KW - Algebra KW - Character generation KW - Computer science KW - Delay KW - formal logic KW - Licenses KW - nondeterminism KW - Process control KW - Protocols KW - Real time systems KW - real-time KW - System testing KW - testing preorders KW - testing theory KW - timed testing KW - Timing KW - timing behavior KW - transition systems AB - A framework for generating testing preorders that relate processes on the basis of their timing behavior as well as their degree of relative nondeterminism is developed. The basic concepts of transition systems and testing are reviewed, and timed testing, which takes account of the delay exhibited by a process as it attempts to pass a test, is introduced. The framework is then applied to two different scenarios. In the first, relations are constructed that relate processes on the basis of all timing considerations. In the second, relations are constructed that relate processes on the basis of their relative speeds. In both cases, alternative denotational characterizations of the resulting preorders are presented, and examples are given to illustrate the utility of the approach JA - , Proceedings of Sixth Annual IEEE Symposium on Logic in Computer Science, 1991. LICS '91 PB - IEEE SN - 0-8186-2230-X M3 - 10.1109/LICS.1991.151635 ER - TY - JOUR T1 - Timing Requirements for Time-Driven Systems Using Augmented Petri Nets JF - IEEE Transactions on Software Engineering Y1 - 1983 A1 - Coolahan,J. E. A1 - Roussopoulos, Nick KW - Application software KW - Concurrent computing KW - Control systems KW - Embedded computing KW - Embedded system KW - Helium KW - Modeling methodology KW - performance specifications KW - Petri nets KW - Power system modeling KW - Real time systems KW - real-time systems KW - Timing KW - timing requirements AB - A methodology for the statement of timing requirements is presented for a class of embedded computer systems. The notion of a "time-driven" system is introduced which is formalized using a Petri net model augmented with timing information. Several subclasses of time-driven systems are defined with increasing levels of complexity. By deriving the conditions under which the Petri net model can be proven to be safe in the presence of time, timing requirements for modules in the system can be obtained. Analytical techniques are developed for proving safeness in the presence of time for the net constructions used in the defined subclasses of time-driven systems. VL - SE-9 SN - 0098-5589 CP - 5 M3 - 10.1109/TSE.1983.235261 ER -