TY - CONF T1 - Towards On-chip Fault-tolerant Communication T2 - ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference Y1 - 2003 A1 - Tudor Dumitras A1 - Kerner, Sam A1 - M\uarculescu, Radu AB - As CMOS technology scales down into the deep-submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. Relaxing the requirement of 100% correctness in operation drastically reduces the costs of design but, at the same time, requires SoCs be designed with some degree of system-level fault-tolerance. In this paper, we introduce a high-level model of DSM failure patterns and propose a new communication paradigm for SoCs, namely stochastic communication. Specifically, for a generic tile-based architecture, we propose a randomized algorithm which not only separates computation from communication, but also provides the required fault-tolerance to on-chip failures. This new technique is easy and cheap to implement in SoCs that integrate a large number of communicating IP cores. JA - ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference T3 - ASP-DAC '03 PB - ACM SN - 0-7803-7660-9 UR - http://doi.acm.org/10.1145/1119772.1119817 ER -