@conference {19261,
	title = {Modeling and optimization of dynamic signal processing in resource-aware sensor networks},
	booktitle = {2011 8th IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS)},
	year = {2011},
	month = {2011},
	pages = {449 - 454},
	abstract = {Sensor node processing in resource-aware sensor networks is often critically dependent on dynamic signal processing functionality - i.e., signal processing functionality in which computational structure must be dynamically assessed and adapted based on time-varying environmental conditions, operating constraints or application requirements. In dynamic signal processing systems, it is important to provide flexibility for run-time adaptation of application behavior and execution characteristics, but in the domain of resource-aware sensor networks, such flexibility cannot come with significant costs in terms of power consumption overhead or reduced predictability. In this paper, we review a variety of complementary models of computation that are being developed as part of the dataflow interchange format (DIF) project to facilitate efficient and reliable implementation of dynamic signal processing systems. We demonstrate these methods in the context of resource-aware sensor networks.},
	keywords = {Adaptation models, Aerodynamics, Computational modeling, data flow graphs, dataflow interchange format, Dynamic scheduling, dynamic signal processing, power consumption overhead, Program processors, resource-aware sensor networks, run-time adaptation, Schedules, sensor node processing, Signal processing, Wireless sensor networks},
	author = {Bhattacharyya, Shuvra S. and Plishker,W. and Sane, N. and Chung-Ching Shen and Wu, Hsiang-Huang}
}
@conference {19295,
	title = {Buffer management for multi-application image processing on multi-core platforms: Analysis and case study},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1662 - 1665},
	abstract = {Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly- arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.},
	keywords = {block-based image data, buffer memory management, buffer storage, concurrently-executing image processing application, data flow computing, data flow representation, data subset, Dataflow, Digital signal processing, Energy consumption, Energy management, Engineering management, FIFO buffer sizes, Hardware, Image analysis, IMAGE PROCESSING, image processing application, image representation, interprocessor communication, memory architecture, Memory management, multiapplication image processing, multicore image processing, multiprocessing, on-chip memory, power consumption, power consumption overhead, Runtime, scheduling, set theory, shared memory, storage management chips, synchronization overhead},
	author = {Ko,Dong-Ik and Won, N. and Bhattacharyya, Shuvra S.}
}
