@article {19253,
	title = {Design and Synthesis for Multimedia Systems Using the Targeted Dataflow Interchange Format},
	journal = {IEEE Transactions on Multimedia},
	volume = {14},
	year = {2012},
	month = {2012},
	pages = {630 - 640},
	abstract = {Development of multimedia systems that can be targeted to different platforms is challenging due to the need for rigorous integration between high-level abstract modeling, and low-level synthesis and optimization. In this paper, a new dataflow-based design tool called the targeted dataflow interchange format is introduced for retargetable design, analysis, and implementation of embedded software for multimedia systems. Our approach provides novel capabilities, based on principles of task-level dataflow analysis, for exploring and optimizing interactions across design components; object-oriented data structures for encapsulating contextual information for components; a novel model for representing parameterized schedules that are derived from repetitive graph structures; and automated code generation for programming interfaces and low-level customizations that are geared toward high-performance embedded-processing architectures. We demonstrate our design tool for cross-platform application design, parameterized schedule representation, and associated dataflow graph-code generation using a case study centered around an image registration application.},
	keywords = {associated dataflow graph-code generation, Computational modeling, contextual information encapsulation, cross-platform application design, data flow graphs, Data models, Data structures, Dataflow graphs, design components, design tools, Digital signal processing, electronic data interchange, embedded signal processing, Embedded software, high-level abstract modeling, high-performance embedded-processing architectures, Image coding, image registration application, image representation, low-level customizations, low-level optimization, low-level synthesis, Multimedia communication, multimedia systems, multimedia systems development, object-oriented data structures, object-oriented methods, parameterized schedule representation, programming interfaces, repetitive graph structures, retargetable design, Schedules, scheduling, software synthesis, Streaming media, targeted dataflow interchange format, task-level dataflow analysis},
	isbn = {1520-9210},
	author = {Chung-Ching Shen and Wu, Shenpei and Sane, N. and Wu, Hsiang-Huang and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19263,
	title = {A design tool for efficient mapping of multimedia applications onto heterogeneous platforms},
	booktitle = {2011 IEEE International Conference on Multimedia and Expo (ICME)},
	year = {2011},
	month = {2011},
	pages = {1 - 6},
	abstract = {Development of multimedia systems on heterogeneous platforms is a challenging task with existing design tools due to a lack of rigorous integration between high level abstract modeling, and low level synthesis and analysis. In this paper, we present a new dataflow-based design tool, called the targeted dataflow interchange format (TDIF), for design, analysis, and implementation of embedded software for multimedia systems. Our approach provides novel capabilities, based on the principles of task-level dataflow analysis, for exploring and optimizing interactions across application behavior; operational context; heterogeneous platforms, including high performance embedded processing architectures; and implementation constraints.},
	keywords = {Dataflow graphs, design tools, embedded signal processing, software synthesis},
	author = {Chung-Ching Shen and Wu, Hsiang-Huang and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19297,
	title = {FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1510 - 1513},
	abstract = {Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications. In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically. However, the potential to enable efficient hardware synthesis has been treated relatively sparsely in the literature for SDF and even more so for the newer, more general PSDF model. This paper investigates efficient FPGA-based design and implementation of the physical layer for 3GPP-Long Term Evolution (LTE), a next generation cellular standard. To capture the SDF behavior of the functional core of LTE along with higher level dynamics in the standard, we use a novel PSDF-based FPGA architecture framework. We implement our PSDF-based, LTE design framework using National Instrument{\textquoteright}s LabVIEW FPGA, a recently-introduced commercial platform for reconfigurable hardware implementation. We show that our framework can effectively model the dynamics of the LTE protocol, while also providing a synthesis framework for efficient FPGA implementation.},
	keywords = {3G mobile communication, 3GPP-long term evolution, 3GPP-LTE physical layer, 4G communication systems, Computational modeling, data flow analysis, data flow graphs, Dataflow modeling, Digital signal processing, DSP applications, Field programmable gate arrays, FPGA architecture framework, FPGA implementation, FPGA-based design, Hardware, hardware synthesis, Instruments, LabVIEW FPGA, Logic Design, LTE, next generation cellular standard, parameterized synchronous data flow technique, Pervasive computing, Physical layer, Physics computing, Production, PSDF graph, reconfigurable hardware implementation, Runtime, software synthesis, Ubiquitous Computing, ubiquitous data flow model},
	author = {Kee, Hojin and Bhattacharyya, Shuvra S. and Wong, I. and Yong Rao}
}
