@article {19253,
	title = {Design and Synthesis for Multimedia Systems Using the Targeted Dataflow Interchange Format},
	journal = {IEEE Transactions on Multimedia},
	volume = {14},
	year = {2012},
	month = {2012},
	pages = {630 - 640},
	abstract = {Development of multimedia systems that can be targeted to different platforms is challenging due to the need for rigorous integration between high-level abstract modeling, and low-level synthesis and optimization. In this paper, a new dataflow-based design tool called the targeted dataflow interchange format is introduced for retargetable design, analysis, and implementation of embedded software for multimedia systems. Our approach provides novel capabilities, based on principles of task-level dataflow analysis, for exploring and optimizing interactions across design components; object-oriented data structures for encapsulating contextual information for components; a novel model for representing parameterized schedules that are derived from repetitive graph structures; and automated code generation for programming interfaces and low-level customizations that are geared toward high-performance embedded-processing architectures. We demonstrate our design tool for cross-platform application design, parameterized schedule representation, and associated dataflow graph-code generation using a case study centered around an image registration application.},
	keywords = {associated dataflow graph-code generation, Computational modeling, contextual information encapsulation, cross-platform application design, data flow graphs, Data models, Data structures, Dataflow graphs, design components, design tools, Digital signal processing, electronic data interchange, embedded signal processing, Embedded software, high-level abstract modeling, high-performance embedded-processing architectures, Image coding, image registration application, image representation, low-level customizations, low-level optimization, low-level synthesis, Multimedia communication, multimedia systems, multimedia systems development, object-oriented data structures, object-oriented methods, parameterized schedule representation, programming interfaces, repetitive graph structures, retargetable design, Schedules, scheduling, software synthesis, Streaming media, targeted dataflow interchange format, task-level dataflow analysis},
	isbn = {1520-9210},
	author = {Chung-Ching Shen and Wu, Shenpei and Sane, N. and Wu, Hsiang-Huang and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19263,
	title = {A design tool for efficient mapping of multimedia applications onto heterogeneous platforms},
	booktitle = {2011 IEEE International Conference on Multimedia and Expo (ICME)},
	year = {2011},
	month = {2011},
	pages = {1 - 6},
	abstract = {Development of multimedia systems on heterogeneous platforms is a challenging task with existing design tools due to a lack of rigorous integration between high level abstract modeling, and low level synthesis and analysis. In this paper, we present a new dataflow-based design tool, called the targeted dataflow interchange format (TDIF), for design, analysis, and implementation of embedded software for multimedia systems. Our approach provides novel capabilities, based on the principles of task-level dataflow analysis, for exploring and optimizing interactions across application behavior; operational context; heterogeneous platforms, including high performance embedded processing architectures; and implementation constraints.},
	keywords = {Dataflow graphs, design tools, embedded signal processing, software synthesis},
	author = {Chung-Ching Shen and Wu, Hsiang-Huang and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@article {19256,
	title = {Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs},
	journal = {Journal of Signal Processing Systems},
	volume = {65},
	year = {2011},
	month = {2011},
	pages = {229 - 244},
	abstract = {Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language{\textemdash}a language for specifying DSP-oriented dataflow graphs{\textemdash}with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.},
	keywords = {Circuits and Systems, Computer Imaging, Vision, Pattern Recognition and Graphics, Dataflow graphs, Electrical Engineering, High-level languages, Image Processing and Computer Vision, model-based design, pattern recognition, Signal processing systems, Signal, Image and Speech Processing, Topological patterns},
	isbn = {1939-8018, 1939-8115},
	url = {http://link.springer.com/article/10.1007/s11265-011-0610-1},
	author = {Sane, Nimish and Kee, Hojin and Seetharaman, Gunasekaran and Bhattacharyya, Shuvra S.}
}
@conference {19285,
	title = {Scalable representation of dataflow graph structures using topological patterns},
	booktitle = {2010 IEEE Workshop on Signal Processing Systems (SIPS)},
	year = {2010},
	month = {2010},
	pages = {13 - 18},
	abstract = {Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the DIF language - a language for specifying DSP-oriented dataflow graphs - with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.},
	keywords = {arrays, data flow graphs, Dataflow graphs, DIF language, Digital signal processing, directed graphs, DSP specification languages, embedded signal processing design flows, embedded systems, Field programmable gate arrays, graphical user interface, Graphical user interfaces, High-level languages, modelbased design, optimisation, optimizations, scalable dataflow graph structures representation, semantics, Signal processing, Signal processing systems, Specification languages, text based languages, Topological patterns, Topology, Transform coding},
	author = {Sane, N. and Kee, Hojin and Seetharaman, G. and Bhattacharyya, Shuvra S.}
}
