@conference {17998,
	title = {An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing},
	booktitle = {Proceedings of the 45th annual Design Automation Conference},
	series = {DAC {\textquoteright}08},
	year = {2008},
	month = {2008///},
	pages = {435 - 440},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and low latency at relatively high area cost. In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network{\textquoteright}s area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate.},
	keywords = {hybrid networks, mesh-of-trees, on-chip networks},
	isbn = {978-1-60558-115-6},
	doi = {10.1145/1391469.1391583},
	url = {http://doi.acm.org/10.1145/1391469.1391583},
	author = {Balkan,Aydin O. and Gang Qu and Vishkin, Uzi}
}
@conference {18017,
	title = {Arbitrate-and-move primitives for high throughput on-chip interconnection networks},
	booktitle = {Circuits and Systems, 2004. ISCAS {\textquoteright}04. Proceedings of the 2004 International Symposium on},
	volume = {2},
	year = {2004},
	month = {2004/05//},
	pages = {II - 441-4 Vol.2 - II - 441-4 Vol.2},
	abstract = {An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.},
	keywords = {8, arbiter, arbitrate-and-move, architecture;, asynchronous, balanced, binary, circuit, circuit;, circuits;, consumption;, data, explicit, interconnection, interconnections;, leaf, mesh-of-trees, multi-threading;, Multithreading, n-leaf, network;, pipeline, pipelined, power, primitive, processing;, reduced, simulation;, structures;, synchronous, synchrony, system-on-chip;, tree, tree;},
	doi = {10.1109/ISCAS.2004.1329303},
	author = {Balkan,A.O. and Gang Qu and Vishkin, Uzi}
}
