@conference {17979,
	title = {Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture},
	booktitle = {Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on},
	year = {2011},
	month = {2011/05//},
	pages = {1282 - 1291},
	abstract = {The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. This paper presents a publicly available tool chain for XMT, complete with a highly configurable cycle-accurate simulator and an optimizing compiler. The XMT tool chain has matured and has been validated to a point where its description merits publication. In particular, research and experimentation enabled by the tool chain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer{\textquoteright}s workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the dual goal of ease-of-programming and performance. The applicability of our tool chain extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the tool chain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Unobstructed by techniques such as decomposition-first and programming for locality, this environment may be useful in deferring the teaching of these techniques, when desired, to more advanced or platform-specific courses.},
	keywords = {algorithm;XMT, architecture;XMT, architectures;shared, chain;cycle-accurate, compiler;programmer, compilers;parallel, component;shared, computing;optimizing, hardware;shared, many-core, many-core;concurrency, memory, multithreading;general-purpose, PRAM, simulator;ease-of-programming;explicit, systems;, theory;multi-threading;optimising, tool, workflow;programming, XMT},
	doi = {10.1109/IPDPS.2011.270},
	author = {Keceli,F. and Tzannes,A. and Caragea,G.C. and Barua,R. and Vishkin, Uzi}
}
@conference {17984,
	title = {Resource-Aware Compiler Prefetching for Many-Cores},
	booktitle = {Parallel and Distributed Computing (ISPDC), 2010 Ninth International Symposium on},
	year = {2010},
	month = {2010/07//},
	pages = {133 - 140},
	abstract = {Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor lighter cores with less resources. Support for hardware and software prefetch increase MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We show that in situations where not enough resources are available to issue prefetch instructions for all references in a loop, it is more beneficial to decrease the prefetch distance and prefetch for as many references as possible, rather than use a fixed prefetched distance and skip prefetching for some references, as in current approaches. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15\% and the state-of-the art GCC implementation by up to 34.79\%. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show improvements of up to 24.61\%.},
	keywords = {algorithm;memory, architecture;hardware-software, architectures;parallel, architectures;resource, aware, caches;super-scalar, compiler, compiler;Multicore, compilers;parallel, GCC-derived, level, management;, many-core, memories;storage, out-of-order, Parallel, parallelism;parallel, prefetch;loop, prefetching, prefetching;shared, processor;fine-grained, processors;multiprocessing, systems;optimising},
	doi = {10.1109/ISPDC.2010.16},
	author = {Caragea,G.C. and Tzannes,A. and Keceli,F. and Barua,R. and Vishkin, Uzi}
}
