@conference {19270,
	title = {A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs},
	booktitle = {2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)},
	year = {2011},
	month = {2011},
	pages = {70 - 81},
	abstract = {Dataflow-based application specifications are widely used in model-based design methodologies for signal processing systems. In this paper, we develop a new model called the dataflow schedule graph (DSG) for representing a broad class of dataflow graph schedules. The DSG provides a graphical representation of schedules based on dataflow semantics. In conventional approaches, applications are represented using dataflow graphs, whereas schedules for the graphs are represented using specialized notations, such as various kinds of sequences or looping constructs. In contrast, the DSG approach employs dataflow graphs for representing both application models and schedules that are derived from them. Our DSG approach provides a precise, formal framework for unambiguously representing, analyzing, manipulating, and interchanging schedules. We develop detailed formulations of the DSG representation, and present examples and experimental results that demonstrate the utility of DSGs in the context of heterogeneous signal processing system design.},
	keywords = {Computational modeling, data flow graphs, dataflow schedule graph, dataflow semantics, dataflow-based application specifications, Dynamic scheduling, heterogeneous mapping, heterogeneous signal processing system design, model-based design methodologies, model-based schedule representation, Processor scheduling, Program processors, Schedules, semantics, Signal processing, synchronization},
	author = {Wu, Hsiang-Huang and Chung-Ching Shen and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19261,
	title = {Modeling and optimization of dynamic signal processing in resource-aware sensor networks},
	booktitle = {2011 8th IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS)},
	year = {2011},
	month = {2011},
	pages = {449 - 454},
	abstract = {Sensor node processing in resource-aware sensor networks is often critically dependent on dynamic signal processing functionality - i.e., signal processing functionality in which computational structure must be dynamically assessed and adapted based on time-varying environmental conditions, operating constraints or application requirements. In dynamic signal processing systems, it is important to provide flexibility for run-time adaptation of application behavior and execution characteristics, but in the domain of resource-aware sensor networks, such flexibility cannot come with significant costs in terms of power consumption overhead or reduced predictability. In this paper, we review a variety of complementary models of computation that are being developed as part of the dataflow interchange format (DIF) project to facilitate efficient and reliable implementation of dynamic signal processing systems. We demonstrate these methods in the context of resource-aware sensor networks.},
	keywords = {Adaptation models, Aerodynamics, Computational modeling, data flow graphs, dataflow interchange format, Dynamic scheduling, dynamic signal processing, power consumption overhead, Program processors, resource-aware sensor networks, run-time adaptation, Schedules, sensor node processing, Signal processing, Wireless sensor networks},
	author = {Bhattacharyya, Shuvra S. and Plishker,W. and Sane, N. and Chung-Ching Shen and Wu, Hsiang-Huang}
}
@conference {14736,
	title = {State transfer for clear and efficient runtime updates},
	booktitle = {2011 IEEE 27th International Conference on Data Engineering Workshops (ICDEW)},
	year = {2011},
	month = {2011/04/11/16},
	pages = {179 - 184},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Dynamic software updating (DSU), the practice of updating software while it executes, is a lively area of research. The DSU approach most prominent in both commercial and research systems is in-place updating, in which patches containing program modifications are loaded into a running process. However, in-place updating suffers from several problems: it requires complex tool support, it may adversely affect the performance of normal execution, it requires challenging reasoning to understand the behavior of an updated program, and it requires extra effort to modify program state to be compatible with an update. This paper presents preliminary work investigating the potential for state transfer updating to address these problems. State transfer updates work by launching a new process running the updated program version and transferring program state from the running process to the updated version. In this paper, we describe the use and implementation of Ekiden, a new state transfer updating library for C/C++ programs. Ekiden seeks to redress the difficulties of in-place updating, and we report on our experience updating VSFTPD using Ekiden. This initial experience suggests that state transfer provides the availability benefits of in-place DSU approaches while addressing many of their shortcomings.},
	keywords = {C++ language, C++ program, Cognition, complex tool support, dynamic software updating, efficient runtime update, in-place DSU approach, Libraries, Operating systems, program modification, Program processors, program transfer, program version, Runtime, servers, software libraries, Software maintenance, state transfer update, Steady-state, updating library, VSFTPD},
	isbn = {978-1-4244-9195-7},
	doi = {10.1109/ICDEW.2011.5767632},
	author = {Hayden,C.M. and Smith,E. K and Hicks, Michael W. and Foster, Jeffrey S.}
}
@conference {19286,
	title = {Methods for efficient implementation of Model Predictive Control on multiprocessor systems},
	booktitle = {2010 IEEE International Conference on Control Applications (CCA)},
	year = {2010},
	month = {2010},
	pages = {1357 - 1362},
	abstract = {Model Predictive Control (MPC) has been used in a wide range of application areas including chemical engineering, food processing, automotive engineering, aerospace, and metallurgy. An important limitation on the application of MPC is the difficulty in completing the necessary computations within the sampling interval. Recent trends in computing hardware towards greatly increased parallelism offer a solution to this problem. This paper describes modeling and analysis tools to facilitate implementing the MPC algorithms on parallel computers, thereby greatly reducing the time needed to complete the calculations. The use of these tools is illustrated by an application to a class of MPC problems.},
	keywords = {Computational modeling, COMPUTERS, Equations, Hardware, Linear systems, Mathematical model, model predictive control, MPC algorithms, Multiprocessing systems, Multiprocessor systems, parallel computers, predictive control, Program processors},
	author = {Gu, Ruirui and Bhattacharyya, Shuvra S. and Levine,W. S}
}
@conference {18471,
	title = {Creation of virtual auditory spaces},
	booktitle = {2002 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)},
	volume = {2},
	year = {2002},
	month = {2002/05//},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {High-quality virtual audio scene rendering is a must for emerging virtual/augmented reality applications and for perceptual user interfaces. We describe algorithms for creation of virtual auditory spaces using measured and non-individualized HRTFs and head tracking. Details of algorithms for HRTF interpolation, room impulse response creation, and audio scene presentation are presented. Tests show that individuals externalize well, and find our interface natural. The system runs in real time with latency of less than 30 ms on an office PC without specialized DSP.},
	keywords = {accuracy, Estimation, Finite impulse response filter, Heating, Program processors, Rendering (computer graphics), System-on-a-chip},
	isbn = {0-7803-7402-9},
	doi = {10.1109/ICASSP.2002.5745052},
	author = {Zotkin,Dmitry N and Duraiswami, Ramani and Davis, Larry S.}
}
@conference {14813,
	title = {MDL: a language and compiler for dynamic program instrumentation},
	booktitle = {, 1997 International Conference on Parallel Architectures and Compilation Techniques., 1997. Proceedings},
	year = {1997},
	month = {1997/11/10/14},
	pages = {201 - 212},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {We use a form of dynamic code generation, called dynamic instrumentation, to collect data about the execution of an application program. Dynamic instrumentation allows us to instrument running programs to collect performance and other types of information. The instrumentation code is generated incrementally and can be inserted and removed at any time. Our instrumentation currently runs on the SPARC, PA-RISC, Power 2, Alpha, and x86 architectures. Specification of what data to collect are written in a specialized language called the Metric Description Language, that is part of the Paradyn Parallel Performance Tools. This language allows platform independent descriptions of how to collect performance data. It also provides a concise way to specify, how to constrain performance data to particular resources such as modules, procedures, nodes, files, or message channels (or combinations of these resources). We also describe the details of how we weave instrumentation into a running program},
	keywords = {Alpha architecture, application program, application program interfaces, Application software, compiler generators, Computer science, dynamic code generation, Dynamic compiler, dynamic program instrumentation, Educational institutions, files, instrumentation code, Instruments, MDL, measurement, message channels, Message passing, Metric Description Language, modules, nodes, Operating systems, optimising compilers, PA-RISC, Paradyn Parallel Performance Tools, Parallel architectures, parallel programming, performance data, platform independent descriptions, Power 2 architecture, Power generation, procedures, program debugging, Program processors, running programs, Runtime, software metrics, SPARC, Specification languages, x86 architecture},
	isbn = {0-8186-8090-3},
	doi = {10.1109/PACT.1997.644016},
	author = {Hollingsworth, Jeffrey K and Niam, O. and Miller, B. P and Zhichen Xu and Goncalves,M. J.R and Ling Zheng}
}
@article {16378,
	title = {Going beyond integer programming with the Omega test to eliminate false data dependences},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {6},
	year = {1995},
	month = {1995/02//},
	pages = {204 - 211},
	abstract = {Array data dependence analysis methods currently in use generate false dependences that can prevent useful program transformations. These false dependences arise because the questions asked are conservative approximations to the questions we really should be asking. Unfortunately, the questions we really should be asking go beyond integer programming and require decision procedures for a subclass of Presburger formulas. In this paper, we describe how to extend the Omega test so that it can answer these queries and allow us to eliminate these false data dependences. We have implemented the techniques described here and believe they are suitable for use in production compilers},
	keywords = {Algorithm design and analysis, Arithmetic, Computer science, Data analysis, false data dependences, integer programming, Linear programming, Omega test, Privatization, Production, production compilers, program compilers, Program processors, program testing, program transformations, Testing},
	isbn = {1045-9219},
	doi = {10.1109/71.342135},
	author = {Pugh, William and Wonnacott,D.}
}
@article {17839,
	title = {An integrated runtime and compile-time approach for parallelizing structured and block structured applications},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {6},
	year = {1995},
	month = {1995/07//},
	pages = {747 - 754},
	abstract = {In compiling applications for distributed memory machines, runtime analysis is required when data to be communicated cannot be determined at compile-time. One such class of applications requiring runtime analysis is block structured codes. These codes employ multiple structured meshes, which may be nested (for multigrid codes) and/or irregularly coupled (called multiblock or irregularly coupled regular mesh problems). In this paper, we present runtime and compile-time analysis for compiling such applications on distributed memory parallel machines in an efficient and machine-independent fashion. We have designed and implemented a runtime library which supports the runtime analysis required. The library is currently implemented on several different systems. We have also developed compiler analysis for determining data access patterns at compile time and inserting calls to the appropriate runtime routines. Our methods can be used by compilers for HPF-like parallel programming languages in compiling codes in which data distribution, loop bounds and/or strides are unknown at compile-time. To demonstrate the efficacy of our approach, we have implemented our compiler analysis in the Fortran 90D/HPF compiler developed at Syracuse University. We have experimented with a multi-bloc Navier-Stokes solver template and a multigrid code. Our experimental results show that our primitives have low runtime communication overheads and the compiler parallelized codes perform within 20\% of the codes parallelized by manually inserting calls to the runtime library},
	keywords = {Bandwidth, block structured applications, block structured codes, compile-time approach, compiling applications, data access patterns, Data analysis, Delay, distributed memory machines, distributed memory systems, FORTRAN, Fortran 90D/HPF compiler, High performance computing, HPF-like parallel programming languages, integrated runtime approach, irregularly coupled regular mesh problems, multigrid code, Navier-Stokes solver template, Parallel machines, parallel programming, Pattern analysis, performance evaluation, program compilers, Program processors, Runtime library, Uninterruptible power systems},
	isbn = {1045-9219},
	doi = {10.1109/71.395403},
	author = {Agrawal,G. and Sussman, Alan and Saltz, J.}
}
@article {16751,
	title = {SEES{\textemdash}A Software testing Environment Support System},
	journal = {IEEE Transactions on Software Engineering},
	volume = {SE-11},
	year = {1985},
	month = {1985/04//},
	pages = {355 - 366},
	abstract = {SEES is a database system to support program testing. The program database is automatically created during the compilation of the program by a compiler built using the YACC compiler-compiler.},
	keywords = {Computer architecture, Database systems, Error correction, Program processors, Programming profession, Relational databases, Software testing, software tools, Workstations, Writing},
	isbn = {0098-5589},
	doi = {10.1109/TSE.1985.232225},
	author = {Roussopoulos, Nick and Yeh,R. T}
}
