@conference {12648,
	title = {Algorithmic and architectural design methodology for particle filters in hardware},
	booktitle = {Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on},
	year = {2005},
	month = {2005/10//},
	pages = {275 - 280},
	abstract = {In this paper, we present algorithmic and architectural methodology for building particle filters in hardware. Particle filtering is a new paradigm for filtering in presence of nonGaussian nonlinear state evolution and observation models. This technique has found wide-spread application in tracking, navigation, detection problems especially in a sensing environment. So far most particle filtering implementations are not lucrative for real time problems due to excessive computational complexity involved. In this paper, we re-derive the particle filtering theory to make it more amenable to simplified VLSI implementations. Furthermore, we present and analyze pipelined architectural methodology for designing these computational blocks. Finally, we present an application using the bearing only tracking problem and evaluate the proposed architecture and algorithmic methodology.},
	keywords = {(numerical, algorithmic, architectural, architectures;, bearing, complexity;, computational, design, digital, evolution;, Filtering, filtering;, filters;, implementation;, methodology;, methods);, nonGaussian, nonlinear, only, Parallel, particle, pipeline, pipelined, problem;, processing;, state, tracking, VLSI, VLSI;},
	doi = {10.1109/ICCD.2005.20},
	author = {Sankaranarayanan,A. C and Chellapa, Rama and Srivastava, A.}
}
@conference {18017,
	title = {Arbitrate-and-move primitives for high throughput on-chip interconnection networks},
	booktitle = {Circuits and Systems, 2004. ISCAS {\textquoteright}04. Proceedings of the 2004 International Symposium on},
	volume = {2},
	year = {2004},
	month = {2004/05//},
	pages = {II - 441-4 Vol.2 - II - 441-4 Vol.2},
	abstract = {An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.},
	keywords = {8, arbiter, arbitrate-and-move, architecture;, asynchronous, balanced, binary, circuit, circuit;, circuits;, consumption;, data, explicit, interconnection, interconnections;, leaf, mesh-of-trees, multi-threading;, Multithreading, n-leaf, network;, pipeline, pipelined, power, primitive, processing;, reduced, simulation;, structures;, synchronous, synchrony, system-on-chip;, tree, tree;},
	doi = {10.1109/ISCAS.2004.1329303},
	author = {Balkan,A.O. and Gang Qu and Vishkin, Uzi}
}
