@article {19254,
	title = {Prototyping scalable digital signal processing systems for radio astronomy using dataflow models},
	journal = {Radio Science},
	volume = {47},
	year = {2012},
	month = {2012},
	pages = {n/a - n/a},
	abstract = {There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer{\textquoteright}s ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called theInterconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decimation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. First, we introduce and demonstrate a dataflow-based design approach using thedataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.},
	keywords = {dataflow models, digital downconverter, Digital signal processing, model-based design, radio astronomy, rapid prototyping},
	isbn = {1944-799X},
	url = {http://onlinelibrary.wiley.com/doi/10.1029/2011RS004924/abstract},
	author = {Sane, N. and Ford, J. and Harris, A. I. and Bhattacharyya, Shuvra S.}
}
@conference {19291,
	title = {Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs},
	booktitle = {2010 21st IEEE International Symposium on Rapid System Prototyping (RSP)},
	year = {2010},
	month = {2010},
	pages = {1 - 7},
	abstract = {Parameterized Synchronous Dataflow (PSDF) has been used previously for abstract scheduling and as a model for architecting embedded software and FPGA implementations. PSDF has been shown to be attractive for these purposes due to its support for flexible dynamic reconfiguration, and efficient quasi-static scheduling. To apply PSDF techniques more deeply into the design flow, support for comprehensive functional simulation and efficient hardware mapping is important. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for developing and experimenting with dataflow-based design techniques for signal processing systems, we have developed a tool for functional simulation of PSDF specifications. This simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on this simulation tool, we also present a systematic design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems for signal processing. We demonstrate capabilities for rapid and accurate prototyping offered by our proposed design methodology, along with its novel support for PSDF-based FPGA system implementation.},
	keywords = {abstract scheduling, Computational modeling, Computer architecture, data flow graphs, dataflow based design, dataflow interchange format, design flow, design language, Digital signal processing, digital signal processing systems, dynamic parameter reconfiguration, Dynamic scheduling, efficient hardware mapping, efficient quasistatic scheduling, Embedded software, embedded systems, Field programmable gate arrays, flexible dynamic reconfiguration, FPGA based systems, FPGA implementations, functional simulation, Hardware, parameterized synchronous dataflow graphs, rapid prototyping, Schedules, scheduling, semantics, simulation tool, software package, systematic design methodology},
	author = {Wu, Hsiang-Huang and Kee, Hojin and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@article {12392,
	title = {Logic foundry: rapid prototyping for FPGA-based DSP systems},
	journal = {EURASIP J. Appl. Signal Process.},
	volume = {2003},
	year = {2003},
	month = {2003/01//},
	pages = {565 - 579},
	abstract = {We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.},
	keywords = {CAD tools, Design methodology, DSP, FPGA, integration, rapid prototyping},
	isbn = {1110-8657},
	doi = {10.1155/S1110865703301039},
	url = {http://dx.doi.org/10.1155/S1110865703301039},
	author = {Spivey,Gary and Bhattacharyya, Shuvra S. and Nakajima,Kazuo}
}
