@conference {12381,
	title = {Exploring the probabilistic design space of multimedia systems},
	booktitle = {14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings},
	year = {2003},
	month = {2003/06/09/11},
	pages = {233 - 240},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {In this paper, we propose the novel concept of probabilistic design for multimedia systems and a methodology to quickly explore such design space at an early design stage. The probabilistic design is motivated by the challenge of how to design, but not over-design, multimedia embedded systems while systematically incorporating such application{\textquoteright}s performance requirements, uncertainties in execution time, and tolerance for reasonable execution failures. Our goal is to bridge the gap between real-time analysis and embedded software implementation for rapid and economic (multimedia) system prototyping. Our method takes advantage of multimedia system{\textquoteright}s unique features mentioned above to relax the rigid hardware requirements for software implementation and eventually avoid over-designing the system.},
	keywords = {economic system prototyping, embedded software implementation, Embedded system, Energy consumption, execution time uncertainties, Hardware, multimedia embedded systems, multimedia system prototyping, multimedia systems, performance requirements, probabilistic design space, rapid system prototyping, Real time systems, real-time analysis, reasonable execution failure tolerance, Resource management, software prototyping, Space exploration, Streaming media, systems analysis, Timing, Uncertainty},
	isbn = {0-7695-1943-1},
	doi = {10.1109/IWRSP.2003.1207053},
	author = {Shaoxiong Hua and Gang Qu and Bhattacharyya, Shuvra S.}
}
@conference {14809,
	title = {Performance measurement using low perturbation and high precision hardware assists},
	booktitle = {, The 19th IEEE Real-Time Systems Symposium, 1998. Proceedings},
	year = {1998},
	month = {1998/12/02/4},
	pages = {379 - 388},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {We present the design and implementation of MultiKron PCI, a hardware performance monitor that can be plugged into any computer with a free PCI bus slot. The monitor provides a series of high-resolution timers, and the ability to monitor the utilization of the PCI bus. We also demonstrate how the monitor can be integrated with online performance monitoring tools such as the Paradyn parallel performance measurement tools to improve the overhead of key timer operations by a factor of 25. In addition, we present a series of case studies using the MultiKron hardware performance monitor to measure and tune high-performance parallel completing applications. By using the monitor, we were able to find and correct a performance bug in a popular implementation of the MPI message passing library that caused some communication primitives to run at one half their potential speed},
	keywords = {Clocks, Computerized monitoring, Counting circuits, Debugging, Hardware, hardware performance monitor, high precision hardware assists, low perturbation, measurement, MPI message passing library, MultiKron hardware performance monitor, MultiKron PCI, NIST, online performance monitoring tools, Paradyn parallel performance measurement tools, PCI bus slot, performance bug, performance evaluation, performance measurement, program debugging, program testing, real-time systems, Runtime, Timing},
	isbn = {0-8186-9212-X},
	doi = {10.1109/REAL.1998.739771},
	author = {Mink, A. and Salamon, W. and Hollingsworth, Jeffrey K and Arunachalam, R.}
}
@conference {12783,
	title = {Verifying an intelligent structural control system: a case study},
	booktitle = {Real-Time Systems Symposium, 1994., Proceedings.},
	year = {1994},
	month = {1994/12/07/9},
	pages = {271 - 275},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Describes the formal verification of the timing properties of the design of an intelligent structural control system using the Concurrency Workbench, an automatic verification tool for finite-state processes. The high-level design of the system is first given in Modechart, a graphical specification language for real-time systems, and then translated into a temporal process algebra supported by the Workbench. The facilities provided by this tool are then used to analyze the system and ultimately show it to be correct},
	keywords = {automatic verification tool, case study, Concurrency Workbench, Distributed computing, Distributed control, distributed processing, finite automata, finite-state processes, formal verification, graphical specification language, high-level design, intelligent control, intelligent structural control system verification, Logic, Modechart, Process algebra, Real time systems, real-time systems, Specification languages, structural engineering computing, temporal logic, temporal process algebra, time-varying systems, Timing, timing properties, visual languages},
	isbn = {0-8186-6600-5},
	doi = {10.1109/REAL.1994.342708},
	author = {Elseaidy,W. M and Cleaveland, Rance and Baugh,J. W.}
}
@conference {12796,
	title = {RTSL: a language for real-time schedulability analysis},
	booktitle = {Real-Time Systems Symposium, 1993., Proceedings.},
	year = {1993},
	month = {1993/12/01/3},
	pages = {274 - 283},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {The paper develops a generalized approach to schedulability analysis that is mathematically founded in a process algebra called RTSL. Within RTSL one may describe the functional behavior, timing behavior, timing constraints (or deadlines), and scheduling discipline for real-time systems. The formal semantics of RTSL then allows the reachable state space of finite state systems to be automatically generated and searched for timing exceptions. We provide a generalized schedulability analysis technique to perform this state-based analysis},
	keywords = {Algebra, Algorithm design and analysis, Dynamic scheduling, Failure analysis, finite state machines, finite state systems, formal logic, formal semantics, functional behavior, generalized approach, generalized schedulability analysis technique, Process algebra, Processor scheduling, reachable state space, Real time systems, real-time schedulability analysis, Real-Time Specification Language, real-time systems, RTSL, scheduling, Scheduling algorithm, scheduling discipline, Specification languages, state-based analysis, State-space methods, Time factors, Timing, timing behavior, timing constraints, timing exceptions},
	isbn = {0-8186-4480-X},
	doi = {10.1109/REAL.1993.393489},
	author = {Fredette,A. N and Cleaveland, Rance}
}
@conference {12836,
	title = {A theory of testing for real-time},
	booktitle = {, Proceedings of Sixth Annual IEEE Symposium on Logic in Computer Science, 1991. LICS {\textquoteright}91},
	year = {1991},
	month = {1991/07/15/18},
	pages = {110 - 119},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {A framework for generating testing preorders that relate processes on the basis of their timing behavior as well as their degree of relative nondeterminism is developed. The basic concepts of transition systems and testing are reviewed, and timed testing, which takes account of the delay exhibited by a process as it attempts to pass a test, is introduced. The framework is then applied to two different scenarios. In the first, relations are constructed that relate processes on the basis of all timing considerations. In the second, relations are constructed that relate processes on the basis of their relative speeds. In both cases, alternative denotational characterizations of the resulting preorders are presented, and examples are given to illustrate the utility of the approach},
	keywords = {Algebra, Character generation, Computer science, Delay, formal logic, Licenses, nondeterminism, Process control, Protocols, Real time systems, real-time, System testing, testing preorders, testing theory, timed testing, Timing, timing behavior, transition systems},
	isbn = {0-8186-2230-X},
	doi = {10.1109/LICS.1991.151635},
	author = {Cleaveland, Rance and Zwarico,A. E}
}
@article {16788,
	title = {Timing Requirements for Time-Driven Systems Using Augmented Petri Nets},
	journal = {IEEE Transactions on Software Engineering},
	volume = {SE-9},
	year = {1983},
	month = {1983/09//},
	pages = {603 - 616},
	abstract = {A methodology for the statement of timing requirements is presented for a class of embedded computer systems. The notion of a "time-driven" system is introduced which is formalized using a Petri net model augmented with timing information. Several subclasses of time-driven systems are defined with increasing levels of complexity. By deriving the conditions under which the Petri net model can be proven to be safe in the presence of time, timing requirements for modules in the system can be obtained. Analytical techniques are developed for proving safeness in the presence of time for the net constructions used in the defined subclasses of time-driven systems.},
	keywords = {Application software, Concurrent computing, Control systems, Embedded computing, Embedded system, Helium, Modeling methodology, performance specifications, Petri nets, Power system modeling, Real time systems, real-time systems, Timing, timing requirements},
	isbn = {0098-5589},
	doi = {10.1109/TSE.1983.235261},
	author = {Coolahan,J. E. and Roussopoulos, Nick}
}
