@article {19293,
	title = {Energy-driven distribution of signal processing applications across wireless sensor networks},
	journal = {ACM Trans. Sen. Netw.},
	volume = {6},
	year = {2010},
	month = {2010},
	pages = {24:1 - 24:32},
	abstract = {Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and low power requirements. Based on the need for extended network lifetimes in WSNs in terms of energy use, the energy efficiency of computation and communication operations in the sensor nodes becomes critical. Digital Signal Processing (DSP) applications typically require intensive data processing operations and as a result are difficult to implement directly in resource-limited WSNs. In this article, we present a novel design methodology for modeling and implementing computationally intensive DSP applications applied to wireless sensor networks. This methodology explores efficient modeling techniques for DSP applications, including data sensing and processing; derives formulations of Energy-Driven Partitioning (EDP) for distributing such applications across wireless sensor networks; and develops efficient heuristic algorithms for finding partitioning results that maximize the network lifetime. To address such an energy-driven partitioning problem, this article provides a new way of aggregating data and reducing communication traffic among nodes based on application analysis. By considering low data token delivery points and the distribution of computation in the application, our approach finds energy-efficient trade-offs between data communication and computation.},
	keywords = {DSP, Energy efficiency, network lifetime, Speech recognition, Wireless sensor networks},
	isbn = {1550-4859},
	url = {http://doi.acm.org/10.1145/1754414.1754420},
	author = {Chung-Ching Shen and Plishker, William L. and Ko,Dong-Ik and Bhattacharyya, Shuvra S. and Goldsman,Neil}
}
@article {12352,
	title = {Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation},
	journal = {IEEE Transactions on Signal Processing},
	volume = {55},
	year = {2007},
	month = {2007/06//},
	pages = {3126 - 3138},
	abstract = {In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression},
	keywords = {Application software, array signal processing, code compression methodology, compact representation, Compaction, data compression, Design automation, Digital signal processing, digital signal processing chips, DSP, DSP hardware, embedded systems, Encoding, Field programmable gate arrays, field-programmable gate arrays (FPGAs), FPGA, Hardware, hierarchical runlength encoding, high-level synthesis, Kahn process, loop-based code compaction, looping construct, parameterized loop schedules, program compilers, reconfigurable design, runlength codes, scheduling, Signal generators, Signal processing, Signal synthesis, software engineering, software implementation, static dataflow models, Very large scale integration, VLSI},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2007.893964},
	author = {Ming-Yung Ko and Zissulescu,C. and Puthenpurayil,S. and Bhattacharyya, Shuvra S. and Kienhuis,B. and Deprettere,E. F}
}
@article {12392,
	title = {Logic foundry: rapid prototyping for FPGA-based DSP systems},
	journal = {EURASIP J. Appl. Signal Process.},
	volume = {2003},
	year = {2003},
	month = {2003/01//},
	pages = {565 - 579},
	abstract = {We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.},
	keywords = {CAD tools, Design methodology, DSP, FPGA, integration, rapid prototyping},
	isbn = {1110-8657},
	doi = {10.1155/S1110865703301039},
	url = {http://dx.doi.org/10.1155/S1110865703301039},
	author = {Spivey,Gary and Bhattacharyya, Shuvra S. and Nakajima,Kazuo}
}
