@conference {19269,
	title = {Applying graphics processor acceleration in a software defined radio prototyping environment},
	booktitle = {2011 22nd IEEE International Symposium on Rapid System Prototyping (RSP)},
	year = {2011},
	month = {2011},
	pages = {67 - 73},
	abstract = {With higher bandwidth requirements and more complex protocols, software defined radio (SDR) has ever growing computational demands. SDR applications have different levels of parallelism that can be exploited on multicore platforms, but design and programming difficulties have inhibited the adoption of specialized multicore platforms like graphics processors (GPUs). In this work we propose a new design flow that augments a popular existing SDR development environment (GNU Radio), with a dataflow foundation and a stand-alone GPU accelerated library. The approach gives an SDR developer the ability to prototype a GPU accelerated application and explore its design space fast and effectively. We demonstrate this design flow on a standard SDR benchmark and show that deciding how to utilize a GPU can be non-trivial for even relatively simple applications.},
	keywords = {Acceleration, coprocessors, dataflow foundation, GNU radio, Graphics processing unit, graphics processor acceleration, Kernel, Libraries, multicore platforms, Multicore processing, PARALLEL PROCESSING, Pipelines, Protocols, software defined radio prototyping environment, software radio, stand-alone GPU accelerated library},
	author = {Plishker,W. and Zaki, G.F. and Bhattacharyya, Shuvra S. and Clancy, C. and Kuykendall, J.}
}
@conference {19259,
	title = {Vectorization and mapping of software defined radio applications on heterogeneous multi-processor platforms},
	booktitle = {2011 IEEE Workshop on Signal Processing Systems (SiPS)},
	year = {2011},
	month = {2011},
	pages = {31 - 36},
	abstract = {A variety of multiprocessor architectures have proliferated even for off-the-shelf computing platforms. To improve performance and productivity for common heterogeneous systems, we have developed a workflow to generate efficient solutions. By starting with a formal description of an application and the mapping problem we are able to generate a range of designs that efficiently trade-of latency and throughput. In this approach, efficient utilization of SIMD cores is achieved by applying extensive block processing in conjunction with efficient mapping and scheduling. We demonstrate our approach through an integration into the GNU Radio environment for software defined radio system design.},
	keywords = {Benchmark testing, block processing, Design methodology, formal description, GNU radio environment, Graphic Processor Unit, Graphics processing unit, heterogeneous multiprocessor platform, mapping problem, Multicore processing, Multiprocessing systems, multiprocessor architecture, multiprocessor scheduling, operating systems (computers), PARALLEL PROCESSING, Processor scheduling, Schedules, SIMD core, Software Defined Radio, software defined radio system design, software radio, telecommunication computing, Throughput, vectorization, workflow},
	author = {Zaki, G.F. and Plishker,W. and Bhattacharyya, Shuvra S. and Clancy, C. and Kuykendall, J.}
}
@conference {19290,
	title = {Loop transformations for interface-based hierarchies IN SDF graphs},
	booktitle = {2010 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP)},
	year = {2010},
	month = {2010},
	pages = {341 - 344},
	abstract = {Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data-flow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy (Interface-based SDF) has been proposed allowing more expressivity while maintaining its predictability. One of the main problems with this hierarchical SDF model is the lack of trade-off between parallelism and network clustering. This paper presents a systematic method for applying an important class of loop transformation techniques in the context of interface-based SDF semantics. The resulting approach provides novel capabilities for integrating parallelism extraction properties of the targeted loop transformations with the useful modeling, analysis, and code reuse properties provided by SDF.},
	keywords = {Application software, code generation, Computer architecture, Computer interfaces, Data-Flow programming, Digital signal processing, Loop parallelization, PARALLEL PROCESSING, Power engineering computing, Power system modeling, Processor scheduling, Programming profession, scheduling, SDF graph, system recovery},
	author = {Piat, J. and Bhattacharyya, Shuvra S. and Raulet, M.}
}
@article {19299,
	title = {Utilizing Hierarchical Multiprocessing for Medical Image Registration},
	journal = {IEEE Signal Processing Magazine},
	volume = {27},
	year = {2010},
	month = {2010},
	pages = {61 - 68},
	abstract = {This work discusses an approach to utilize hierarchical multiprocessing in the context of medical image registration. By first organizing application parallelism into a domain-specific taxonomy, an algorithm is structured to target a set of multicore platforms.The approach on a cluster of graphics processing units (GPUs) requiring the use of two parallel programming environments to achieve fast execution times is demonstrated.There is negligible loss in accuracy for rigid registration when employing GPU acceleration, but it does adversely effect our nonrigid registration implementation due to our usage of a gradient descent approach.},
	keywords = {Acceleration, application parallelism, Biomedical imaging, domain-specific taxonomy, GPU acceleration, gradient descent approach, Graphics processing unit, hierarchical multiprocessing, image registration, Magnetic resonance imaging, Medical diagnostic imaging, medical image processing, medical image registration, multicore platform set, Multicore processing, PARALLEL PROCESSING, parallel programming, Robustness, Signal processing algorithms, Ultrasonic imaging},
	isbn = {1053-5888},
	author = {Plishker,W. and Dandekar,O. and Bhattacharyya, Shuvra S. and Shekhar,R.}
}
@conference {12347,
	title = {A Communication Interface for Multiprocessor Signal Processing Systems},
	booktitle = {Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia},
	year = {2006},
	month = {2006/10//},
	pages = {127 - 132},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Parallelization of embedded software is often desirable for power/performance-related considerations for computation-intensive applications that frequently occur in the signal-processing domain. Although hardware support for parallel computation is increasingly available in embedded processing platforms, there is a distinct lack of effective software support. One of the most widely known efforts in support of parallel software is the message passing interface (MPI). However, MPI suffers from several drawbacks with regards to customization to specialized parallel processing contexts, and performance degradation for communication-intensive applications. In this paper, we propose a new interface, the signal passing interface (SPI), that is targeted toward signal processing applications and addresses the limitations of MPI for this important domain of embedded software by integrating relevant properties of MPI and coarse-grain dataflow modeling. SPI is much easier and more intuitive to use, and due to its careful specialization, more performance-efficient for the targeted application domain. We present our preliminary version of SPI, along with experiments using SPI on a practical face detection system that demonstrate the capabilities of SPI},
	keywords = {application program interfaces, Application software, coarse-grain dataflow modeling, Computer applications, Concurrent computing, Context, data flow graphs, Embedded computing, Embedded software, face detection system, Hardware, Message passing, message passing interface, MPI, Multiprocessing systems, multiprocessor signal processing system, PARALLEL PROCESSING, signal passing interface, Signal processing, SPI},
	isbn = {0-7803-9783-5},
	doi = {10.1109/ESTMED.2006.321285},
	author = {Sankalita Saha and Bhattacharyya, Shuvra S. and Wayne Wolf}
}
@conference {17854,
	title = {Model-based OpenMP implementation of a 3D facial pose tracking system},
	booktitle = {2006 International Conference on Parallel Processing Workshops, 2006. ICPP 2006 Workshops},
	year = {2006},
	month = {2006///},
	pages = {8 pp.-73 - 8 pp.-73},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on shared-memory systems offer an attractive solution to this class of applications. However, we cannot thoroughly exploit the advantages of such architectures without proper modeling and analysis of the application. In this paper, we describe our implementation of a 3D facial pose tracking system using the OpenMP platform. Our implementation is based on a design methodology that uses coarse-grain dataflow graphs to model and schedule the application. We present our modeling approach, details of the implementation that we derived based on this modeling approach, and associated performance results. The parallelized implementation achieves significant speedup, and meets or exceeds the target frame rate under various configurations},
	keywords = {3D facial pose tracking system, application modeling, application program interfaces, application scheduling, coarse-grain dataflow graphs, Concurrent computing, data flow graphs, Educational institutions, face recognition, IMAGE PROCESSING, image processing applications, Inference algorithms, Message passing, OpenMP platform, parallel implementation, PARALLEL PROCESSING, parallel programming, Particle tracking, Processor scheduling, SHAPE, shared memory systems, shared-memory systems, Solid modeling, tracking},
	isbn = {0-7695-2637-3},
	doi = {10.1109/ICPPW.2006.55},
	author = {Saha,S. and Chung-Ching Shen and Chia-Jui Hsu and Aggarwal,G. and Veeraraghavan,A. and Sussman, Alan and Bhattacharyya, Shuvra S.}
}
@conference {14793,
	title = {EMPS: an environment for memory performance studies},
	booktitle = {Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International},
	year = {2005},
	month = {2005/04//},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper describes an overview of environment for memory performance studies (EMPS). EMPS is a framework to allow different data gathering and simulation tools to be composed together to predict the performance of parallel programs on a variety of current and future high end computing (HEC) systems. The framework seeks to combine the automated nature of direct execution simulation with the predictive capabilities of performance modeling.},
	keywords = {Application software, cache storage, Computational modeling, Concurrent computing, data gathering, Delay, digital simulation, Economic forecasting, EMP radiation effects, high end computing system, High performance computing, memory architecture, memory performance, Moore{\textquoteright}s Law, PARALLEL PROCESSING, parallel program, Predictive models, simulation tool, Writing},
	isbn = {0-7695-2312-9},
	doi = {10.1109/IPDPS.2005.196},
	author = {Hollingsworth, Jeffrey K and Snavely, A. and Sbaraglia, S. and Ekanadham, K.}
}
@conference {12393,
	title = {Systematic exploitation of data parallelism in hardware synthesis of DSP applications},
	booktitle = {Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP {\textquoteright}04). IEEE International Conference on},
	volume = {5},
	year = {2004},
	month = {2004/05//},
	pages = {V - 229-32 vol.5 - V - 229-32 vol.5},
	abstract = {We describe an approach that we have explored for low-power synthesis and optimization of image, video, and digital signal processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in a dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and, based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit.},
	keywords = {area-performance trade-off curve, automatic Verilog code generation, circuit optimisation, data flow graphs, data parallelism, dedicated hardware implementation synthesis, design tool, Digital signal processing, DSP applications, embedded systems, hardware description languages, hardware synthesis, high level synthesis, high level synthesis algorithm, IMAGE PROCESSING, PARALLEL PROCESSING, power consumption, Signal processing, synchronous dataflow graph, video processing},
	doi = {10.1109/ICASSP.2004.1327089},
	author = {Sen,M. and Bhattacharyya, Shuvra S.}
}
@article {17865,
	title = {Processing large-scale multi-dimensional data in parallel and distributed environments},
	journal = {Parallel Computing},
	volume = {28},
	year = {2002},
	month = {2002/05//},
	pages = {827 - 859},
	abstract = {Analysis of data is an important step in understanding and solving a scientific problem. Analysis involves extracting the data of interest from all the available raw data in a dataset and processing it into a data product. However, in many areas of science and engineering, a scientist{\textquoteright}s ability to analyze information is increasingly becoming hindered by dataset sizes. The vast amount of data in scientific datasets makes it a difficult task to efficiently access the data of interest, and manage potentially heterogeneous system resources to process the data. Subsetting and aggregation are common operations executed in a wide range of data-intensive applications. We argue that common runtime and programming support can be developed for applications that query and manipulate large datasets. This paper presents a compendium of frameworks and methods we have developed to support efficient execution of subsetting and aggregation operations in applications that query and manipulate large, multi-dimensional datasets in parallel and distributed computing environments.},
	keywords = {Data-intensive applications, Distributed computing, Multi-dimensional datasets, PARALLEL PROCESSING, Runtime systems},
	isbn = {0167-8191},
	doi = {10.1016/S0167-8191(02)00097-2},
	url = {http://www.sciencedirect.com/science/article/pii/S0167819102000972},
	author = {Beynon,Michael and Chang,Chialin and Catalyurek,Umit and Kurc,Tahsin and Sussman, Alan and Andrade,Henrique and Ferreira,Renato and Saltz,Joel}
}
@article {14775,
	title = {Exploiting fine-grained idle periods in networks of workstations},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {11},
	year = {2000},
	month = {2000/07//},
	pages = {683 - 698},
	abstract = {Studies have shown that for a significant fraction of the time, workstations are idle. In this paper, we present a new scheduling policy called Linger-Longer that exploits the fine-grained availability of workstations to run sequential and parallel jobs. We present a two-level workload characterization study and use it to simulate a cluster of workstations running our new policy. We compare two variations of our policy to two previous policies: Immediate-Eviction and Pause-and-Migrate. Our study shows that the Linger-Longer policy can improve the throughput of foreign jobs on a cluster by 60 percent with only a 0.5 percent slowdown of local jobs. For parallel computing, we show that the Linger-Longer policy outperforms reconfiguration strategies when the processor utilization by the local process is 20 percent or less in both synthetic bulk synchronous and real data-parallel applications},
	keywords = {cluster of workstations, Computer networks, Concurrent computing, Contracts, Delay, fine-grained availability, Intelligent networks, Linger-Longer, networks of workstations, PARALLEL PROCESSING, Predictive models, Processor scheduling, Resumes, scheduling policy, Throughput, workload characterization, workstation clusters, Workstations},
	isbn = {1045-9219},
	doi = {10.1109/71.877793},
	author = {Kyung Dong Ryu and Hollingsworth, Jeffrey K}
}
@conference {17880,
	title = {Optimizing retrieval and processing of multi-dimensional scientific datasets},
	booktitle = {Parallel and Distributed Processing Symposium, 2000. IPDPS 2000. Proceedings. 14th International},
	year = {2000},
	month = {2000///},
	pages = {405 - 410},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {We have developed the Active Data Repository (ADR), an infrastructure that integrates storage, retrieval, and processing of large multi-dimensional scientific datasets on distributed memory parallel machines with multiple disks attached to each node. In earlier work, we proposed three strategies for processing range queries within the ADR framework. Our experimental results show that the relative performance of the strategies changes under varying application characteristics and machine configurations. In this work we investigate approaches to guide and automate the selection of the best strategy for a given application and machine configuration. We describe analytical models to predict the relative performance of the strategies where input data elements are uniformly distributed in the attribute space of the output dataset, restricting the output dataset to be a regular d-dimensional array},
	keywords = {active data repository, Area measurement, Computer science, Data analysis, distributed memory parallel machines, Educational institutions, Information retrieval, Information Storage and Retrieval, infrastructure, Microscopy, Microwave integrated circuits, multi-dimensional scientific datasets retrieval, PARALLEL PROCESSING, Pathology, range queries, regular d-dimensional array, Satellites, Tomography},
	isbn = {0-7695-0574-0},
	doi = {10.1109/IPDPS.2000.846013},
	author = {Chang,Chialin and Kurc, T. and Sussman, Alan and Saltz, J.}
}
@conference {14762,
	title = {Benchmarking a network of PCs running parallel applications},
	booktitle = {Performance, Computing and Communications, 1998. IPCCC {\textquoteright}98., IEEE International},
	year = {1998},
	month = {1998/02/16/18},
	pages = {1 - 7},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Presents a benchmarking study that compares the performance of a network of four PCs connected by a 100 Mbit/s fast Ethernet running three different system software configurations: TCP/IP on Windows NT, TCP/IP on Linux and a lightweight message-passing protocol (U-Net active messages) on Linux. For each configuration, we report results for communication micro-benchmarks and the NAS (Numerical Aerodynamics Simulation) parallel benchmarks. For the NAS benchmarks, the overall running time using Linux TCP/IP was 12-500\% less than the Windows NT TCP/IP configuration. Likewise, the Linux U-Net based message-passing protocol outperformed the Linux TCP/IP version by 5-200\%+. We also show that, by using Linux U-Net, we are able to achieve 125 μs latency between two processes using PVM. Finally, we report that the default mathematical libraries supplied with NT (for both gcc and Visual C++) are substantially slower than the one supplied with Linux},
	keywords = {100 Mbit/s, 125 mus, Aerodynamics, Application software, communication micro-benchmarks, default mathematical libraries, Delay, Ethernet, Ethernet networks, gcc, latency, lightweight message-passing protocol, Linux, Local area networks, mathematics computing, Message passing, microcomputer applications, Microsoft Windows NT, NAS parallel benchmarks, network operating systems, Numerical simulation, parallel applications, PARALLEL PROCESSING, PC network benchmarking, performance comparison, performance evaluation, Personal communication networks, Protocols, PVM, running time, software libraries, System software, system software configurations, TCP/IP, TCPIP, Transport protocols, U-Net active messages, Visual C++},
	isbn = {0-7803-4468-5},
	doi = {10.1109/PCCC.1998.659876},
	author = {Hollingsworth, Jeffrey K and Guven, E. and Akinlar, C.}
}
@article {14804,
	title = {Modeling and evaluating design alternatives for an on-line instrumentation system: a case study},
	journal = {IEEE Transactions on Software Engineering},
	volume = {24},
	year = {1998},
	month = {1998/06//},
	pages = {451 - 470},
	abstract = {This paper demonstrates the use of a model-based evaluation approach for instrumentation systems (ISs). The overall objective of this study is to provide early feedback to tool developers regarding IS overhead and performance; such feedback helps developers make appropriate design decisions about alternative system configurations and task scheduling policies. We consider three types of system architectures: network of workstations (NOW), symmetric multiprocessors (SMP), and massively parallel processing (MPP) systems. We develop a Resource OCCupancy (ROCC) model for an on-line IS for an existing tool and parameterize it for an IBM SP-2 platform. This model is simulated to answer several {\textquotedblleft}what if{\textquotedblright} questions regarding two policies to schedule instrumentation data forwarding: collect-and-forward (CF) and batch-and-forward (BF). In addition, this study investigates two alternatives for forwarding the instrumentation data: direct and binary tree forwarding for an MPP system. Simulation results indicate that the BF policy can significantly reduce the overhead and that the tree forwarding configuration exhibits desirable scalability characteristics for MPP systems. Initial measurement-based testing results indicate more than 60 percent reduction in the direct IS overhead when the BF policy was added to Paradyn parallel performance measurement tool},
	keywords = {alternative system configurations, Application software, batch-and-forward, collect-and-forward, Computer aided software engineering, design alternatives, design decisions, Feedback, IBM SP-2 platform, Instruments, massively parallel processing, model-based evaluation approach, Monitoring, multiprocessing programs, on-line instrumentation system, Paradyn parallel performance measurement tool, PARALLEL PROCESSING, Real time systems, scalability characteristics, software metrics, software tools, Space technology, symmetric multiprocessors, system architectures, system monitoring, System testing, task scheduling policies, tool developers, tree forwarding configuration, Workstations},
	isbn = {0098-5589},
	doi = {10.1109/32.689402},
	author = {Waheed, A. and Rover, D. T and Hollingsworth, Jeffrey K}
}
@conference {16363,
	title = {Code generation for multiple mappings},
	booktitle = {Frontiers of Massively Parallel Computation, 1995. Proceedings. Frontiers {\textquoteright}95., Fifth Symposium on the},
	year = {1995},
	month = {1995/02/06/9},
	pages = {332 - 341},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {There has been a great amount of recent work toward unifying iteration reordering transformations. Many of these approaches represent transformations as affine mappings from the original iteration space to a new iteration space. These approaches show a great deal of promise, but they all rely on the ability to generate code that iterates over the points in these new iteration spaces in the appropriate order. This problem has been fairly well-studied in the case where all statements use the same mapping. We have developed an algorithm for the less well-studied case where each statement uses a potentially different mapping. Unlike many other approaches, our algorithm can also generate code from mappings corresponding to loop blocking. We address the important trade-off between reducing control overhead and duplicating code},
	keywords = {code generation, Computer science, Concurrent computing, control overhead, Educational institutions, iteration reordering transformations, Law, Legal factors, loop blocking, multiple mappings, optimisation, optimising compilers, Optimizing compilers, PARALLEL PROCESSING, Performance analysis, program compilers},
	isbn = {0-8186-6965-9},
	doi = {10.1109/FMPC.1995.380437},
	author = {Kelly,W. and Pugh, William and Rosser,E.}
}
@article {15535,
	title = {Deductive Databases and Knowledge Base Systems.},
	year = {1995},
	month = {1995/03/31/},
	institution = {Department of Computer Science, University of Maryland, College Park},
	abstract = {The following sections describe the research that has been accomplished during the entire grant period form September 1, 1991 to March 31, 1995, with partial support from the Air Force Office of Scientific Research and summarizes the papers, prototype systems and theses produced on the grant. Several major areas will be discussed. These are Cooperative Databases Systems, Combining Knowledge Base Systems, Disjunctive Deduction Databases, Extensions to the Semantics of Logic Programming and Parallel Logic Programming. During the first year of the grant we emphasized theoretical aspects of work in deductive databases and knowledge base systems. During the second year we stressed the development of tools and techniques to transfer the theory into practical systems. During the third year we developed prototype systems and experiments with them. Technological developments were made in Cooperative Database Systems and Disjunctive Deductive Databases. New theoretical developments were achieved in the Semantics of Logic Programming and in Combining Databases.},
	keywords = {*DATA BASES, *KNOWLEDGE BASED SYSTEMS, *RESEARCH MANAGEMENT, *SYSTEMS ENGINEERING, AIR FORCE RESEARCH, COMPUTER LOGIC, COMPUTER PROGRAMMING, COMPUTER PROGRAMMING AND SOFTWARE, COMPUTER SYSTEMS, logic programming, PARALLEL LOGIC PROGRAMMING, PARALLEL PROCESSING, Prototypes, semantics, THESES, TRANSFER., WUAFOSR2304GS},
	url = {http://stinet.dtic.mil/oai/oai?\&verb=getRecord\&metadataPrefix=html\&identifier=ADA295498},
	author = {Minker, Jack}
}
@article {14189,
	title = {A syntactic approach to scale-space-based corner description},
	journal = {IEEE Transactions on Pattern Analysis and Machine Intelligence},
	volume = {16},
	year = {1994},
	month = {1994/07//},
	pages = {748 - 751},
	abstract = {Planar curves are described by information about corners integrated over various levels of resolution. The detection of corners takes place on a digital representation. To compensate for ambiguities arising from sampling problems due to the discreteness, results about the local behavior of curvature extrema in continuous scale-space are employed},
	keywords = {Computer vision, corner detection, curvature extrema, edge detection, IMAGE PROCESSING, image resolution, Image segmentation, Laboratories, Large-scale systems, PARALLEL PROCESSING, pattern recognition, planar curves, resolution, Sampling methods, sampling problems, scale space based corner description, SHAPE, Smoothing methods, syntactic approach},
	isbn = {0162-8828},
	doi = {10.1109/34.297957},
	author = {Ferm{\"u}ller, Cornelia and Kropatsch,W.}
}
@conference {14575,
	title = {Parallel transitive closure computations using topological sort},
	booktitle = {, Proceedings of the First International Conference on Parallel and Distributed Information Systems, 1991},
	year = {1991},
	month = {1991/12/04/6},
	pages = {122 - 129},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Deals with parallel transitive closure computations. The sort-based approaches introduced sorts the tuples of the relation into topological order, and the sorted relation is then horizontally partitioned and distributed across several processing nodes of a message passing multiprocessor system. This data partitioning strategy allows the transitive closure computation of the local data fragments to be computed in parallel with no interprocessor communication. The construction of the final result then requires only a small number of joins. Extensive analytical results are included in the paper as well. They show that the proposed techniques leads to a speedup that is essentially linear with the number of processors. Its performance is significantly better than the recently published hashless parallel algorithm},
	keywords = {Computer science, Concurrent computing, data partitioning, Database systems, database theory, deductive databases, File systems, horizontal partitioning, joins, local data fragments, message passing multiprocessor system, Multiprocessing systems, Parallel algorithms, PARALLEL PROCESSING, parallel programming, parallel transitive closure, processing nodes, relation tuples, Relational databases, sorting, topological sort},
	isbn = {0-8186-2295-4},
	doi = {10.1109/PDIS.1991.183079},
	author = {Hua,K. A and Hannenhalli, Sridhar}
}
