@conference {17979,
	title = {Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture},
	booktitle = {Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on},
	year = {2011},
	month = {2011/05//},
	pages = {1282 - 1291},
	abstract = {The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. This paper presents a publicly available tool chain for XMT, complete with a highly configurable cycle-accurate simulator and an optimizing compiler. The XMT tool chain has matured and has been validated to a point where its description merits publication. In particular, research and experimentation enabled by the tool chain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer{\textquoteright}s workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the dual goal of ease-of-programming and performance. The applicability of our tool chain extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the tool chain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Unobstructed by techniques such as decomposition-first and programming for locality, this environment may be useful in deferring the teaching of these techniques, when desired, to more advanced or platform-specific courses.},
	keywords = {algorithm;XMT, architecture;XMT, architectures;shared, chain;cycle-accurate, compiler;programmer, compilers;parallel, component;shared, computing;optimizing, hardware;shared, many-core, many-core;concurrency, memory, multithreading;general-purpose, PRAM, simulator;ease-of-programming;explicit, systems;, theory;multi-threading;optimising, tool, workflow;programming, XMT},
	doi = {10.1109/IPDPS.2011.270},
	author = {Keceli,F. and Tzannes,A. and Caragea,G.C. and Barua,R. and Vishkin, Uzi}
}
@conference {17989,
	title = {Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer{\textquoteright}s workflow add-on?},
	booktitle = {Computer Design, 2009. ICCD 2009. IEEE International Conference on},
	year = {2009},
	month = {2009/10//},
	pages = {60 - 63},
	abstract = {Our earlier parallel algorithmics work on the parallel random-access-machine/model (PRAM) computation model led us to a PRAM-On-Chip vision: a comprehensive many-core system that can look to the programmer like the abstract PRAM model. We introduced the eXplicit MultiThreaded (XMT) design and prototyped it in hardware and software. XMT comprises a programmer{\textquoteright}s workflow that advances from work-depth, a standard PRAM theory abstraction, to an XMT program, and, if desired, to its performance tuning. XMT provides strong performance for programs developed this way due to its hardware support of very fine-grained threads and the overhead of handling them. XMT has also shown unique promise when it comes to ease-of-programming, the biggest problem that has limited the impact of all parallel systems to date. For example, teachability of XMT programming has been demonstrated at various levels from rising 6<sup>th</sup> graders to graduate students, and students in a freshman class were able to program 3 parallel sorting algorithms. The main purpose of the current paper is to stimulate discussion on the following somewhat open-ended question. Now that we made significant progress on a system devoted to supporting PRAM-like programming, is it possible to incorporate our hardware support as an add-on into other current and future many-core systems? The paper considers a concrete proposal for doing that: recasting our work as a hardware-enhanced programmer{\textquoteright}s workflow {\^A}{\textquestiondown}module{\^A}{\textquestiondown} that can then be essentially imported into the other systems.},
	keywords = {abstraction;PRAM-On-Chip;easy-to-program, algorithms;parallel, algorithms;sorting;, designing;explicit, multi-threading;fine-grained, PRAM, random-access-machine/model;parallel, sorting, system, system;parallel, systems;concurrency, THEORY, theory;multi-threading;parallel, threads;many-core},
	doi = {10.1109/ICCD.2009.5413174},
	author = {Vishkin, Uzi}
}
@conference {17996,
	title = {Fpga-based prototype of a pram-on-chip processor},
	booktitle = {Proceedings of the 5th conference on Computing frontiers},
	series = {CF {\textquoteright}08},
	year = {2008},
	month = {2008///},
	pages = {55 - 66},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel machine model for many years, but it is also believed to be "impossible in reality." As the new billion-transistor processor era begins, the eXplicit Multi-Threading (XMT) PRAM-On-Chip project is attempting to design an on-chip parallel processor that efficiently supports PRAM algorithms. This paper presents the first prototype of the XMT architecture that incorporates 64 simple in-order processors operating at 75MHz. The microarchitecture of the prototype is described and the performance is studied with respect to some micro-benchmarks. Using cycle accurate emulation, the projected performance of an 800MHz XMT ASIC processor is compared with AMD Opteron 2.6GHz, which uses similar area as would a 64-processor ASIC version of the XMT prototype. The results suggest that an only 800MHz XMT ASIC system outperforms AMD Opteron 2.6GHz, with speedups ranging between 1.57 and 8.56.},
	keywords = {ease-of-programming, explicit multi-threading, on-chip parallel processor, Parallel algorithms, PRAM, XMT},
	isbn = {978-1-60558-077-7},
	doi = {10.1145/1366230.1366240},
	url = {http://doi.acm.org/10.1145/1366230.1366240},
	author = {Wen,Xingzhi and Vishkin, Uzi}
}
@article {12109,
	title = {A pilot study to compare programming effort for two parallel programming models},
	journal = {Journal of Systems and Software},
	volume = {81},
	year = {2008},
	month = {2008/11//},
	pages = {1920 - 1930},
	abstract = {ContextWriting software for the current generation of parallel systems requires significant programmer effort, and the community is seeking alternatives that reduce effort while still achieving good performance.
Objective
Measure the effect of parallel programming models (message-passing vs. PRAM-like) on programmer effort.
Design, setting, and subjects
One group of subjects implemented sparse-matrix dense-vector multiplication using message-passing (MPI), and a second group solved the same problem using a PRAM-like model (XMTC). The subjects were students in two graduate-level classes: one class was taught MPI and the other was taught XMTC.
Main outcome measures
Development time, program correctness.
Results
Mean XMTC development time was 4.8\&$\#$xa0;h less than mean MPI development time (95\% confidence interval, 2.0{\textendash}7.7), a 46\% reduction. XMTC programs were more likely to be correct, but the difference in correctness rates was not statistically significant (p\&$\#$xa0;=\&$\#$xa0;.16).
Conclusions
XMTC solutions for this particular problem required less effort than MPI equivalents, but further studies are necessary which examine different types of problems and different levels of programmer experience.
},
	keywords = {effort, empirical study, Message-passing, MPI, parallel programming, PRAM, XMT},
	isbn = {0164-1212},
	doi = {10.1016/j.jss.2007.12.798},
	url = {http://www.sciencedirect.com/science/article/pii/S0164121208000125},
	author = {Hochstein, Lorin and Basili, Victor R. and Vishkin, Uzi and Gilbert,John}
}
@conference {18001,
	title = {PRAM-on-chip: first commitment to silicon},
	booktitle = {Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures},
	series = {SPAA {\textquoteright}07},
	year = {2007},
	month = {2007///},
	pages = {301 - 302},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	keywords = {ease-of-programming, explicit multi-threading, on-chip parallel processor, Parallel algorithms, PRAM, XMT},
	isbn = {978-1-59593-667-7},
	doi = {10.1145/1248377.1248427},
	url = {http://doi.acm.org/10.1145/1248377.1248427},
	author = {Wen,Xingzhi and Vishkin, Uzi}
}
@conference {12115,
	title = {An empirical study to compare two parallel programming models},
	booktitle = {Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures},
	series = {SPAA {\textquoteright}06},
	year = {2006},
	month = {2006///},
	pages = {114 - 114},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {While there are strong beliefs within the community about whether one particular parallel programming model is easier to use than another, there has been little research to analyze these claims empirically. Currently, the most popular paradigm is message-passing, as implemented by the MPI library [1]. However, MPI is considered to be difficult for developing programs, because it forces the programmer to work at a very low level of abstraction. One alternative parallel programming model is the PRAM model, which supports fine-grained parallelism and has a substantial history of algorithmic theory [2]. It is not possible to program current parallel machines using the PRAM model because modern architectures are not designed to support such a model efficiently. However, current trends towards multicore chips suggest that large-scale, fine-grained uniform-memory access parallel machines may soon be feasible. XMT-C is an extension of the C language that supports parallel directives to provide a PRAM-like model to the programmer. A prototype compiler exists that generates code which runs on a simulator for an XMT architecture [3].To better understand how much benefit a PRAM-like model could provide over a message-passing model, we conducted a feasibility study in an academic setting to compare the effort required to solve a particular problem. The questions under study were: can we measure the effort in developing a program using these two programming models and can we differentiate the amount of effort for each model?.The subjects participating in the study were divided up into two groups. One group solved a problem using the MPI library in either C,C++, or Fortran, and the other group solved the problem using XMT-C. The task was to write a function to multiply a sparse matrix with a dense vector. To obtain subjects, we leveraged existing graduate-level parallel programming courses at two different universities: University of California, Santa Barbara (UCSB), and University of Maryland (UMD). At UCSB, the students solved the problem in MPI, and at UMD, the students solved the same problem in XMT-C. The focus of the UCSB class was on developing parallel programs to run on the current generation of architectures, and the students were taught MPI, as well as other models. The focus of the UMD class was parallel algorithms in the PRAM model, and the students were taught XMT-C. The students were assigned to treatment groups by class. The study was integrated into each class, as the problem was a required assignment in each class.Subjects kept track of their effort with a self-reported effort log. We also collected automatic effort data by instrumenting the compilers, which recorded data at each compile. We computed three effort measures: self-reported, instrumented, and combined. Self-reported effort measures are based entirely on effort logs, instrumented effort measures are based entirely on timestamps from the instrumented compilers, and combined effort measures are based on compiler timestamps when the subject is working on the instrumented machine, and self-reported effort when the subject is working off the instrumented machine.The results of this preliminary study answer both of our questions in the positive. In this case, on average, students required less effort to solve the problem using XMT-C compared to MPI. The reduction in mean effort was approximately 50\% for all three measures, which was statistically significant at the level of p < .05 using a t-test.This study demonstrates that the effect of programming model on effort can be directly measured through empirical studies with human subjects. While no single study can conclusively demonstrate the advantage of one programming model over another, a series of studies examining different models and different problems can provide insights into the relative strengths of parallel programming models in different contexts. The study described above is one of a series of such studies that we are currently conducting.},
	keywords = {effort, empirical study, HPC, Message-passing, MPI, parallel programming, PRAM, Productivity, XMT},
	isbn = {1-59593-452-9},
	doi = {10.1145/1148109.1148127},
	url = {http://doi.acm.org/10.1145/1148109.1148127},
	author = {Hochstein, Lorin and Basili, Victor R.}
}
